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indentation

This commit is contained in:
Sebastien Bourdeauducq 2015-06-17 08:32:17 -06:00
parent c0bc94ca1c
commit 7c2d0fa641
1 changed files with 1 additions and 1 deletions
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misoclib/soc/sdram.py
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@ -54,7 +54,7 @@ class SDRAMSoC(SoC):
main_ram_size = min(main_ram_size, 256*1024*1024) main_ram_size = min(main_ram_size, 256*1024*1024)
l2_size = self.sdram_controller_settings.l2_size l2_size = self.sdram_controller_settings.l2_size
# add a wishbone interface to the DRAM # add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()
self.add_wb_sdram_if(wb_sdram) self.add_wb_sdram_if(wb_sdram)
self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size) self.register_mem("main_ram", self.mem_map["main_ram"], wb_sdram, main_ram_size)