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dvisampler/datacapture: deserialize to 10 bits

This commit is contained in:
Sebastien Bourdeauducq 2013-03-21 19:06:15 +01:00
parent fa2331e084
commit 7c4ca4fd66
2 changed files with 22 additions and 9 deletions
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5
milkymist/dvisampler/__init__.py
View File

@ -17,9 +17,10 @@ class DVISampler(Module, AutoReg):
for datan in "012": for datan in "012":
name = "data" + str(datan) name = "data" + str(datan)
cap = DataCapture(8) invert = datan in inversions
cap = DataCapture(8, invert)
setattr(self.submodules, name + "_cap", cap) setattr(self.submodules, name + "_cap", cap)
if datan in inversions: if invert:
name += "_n" name += "_n"
s = Signal(name=name) s = Signal(name=name)
setattr(self, name, s) setattr(self, name, s)

26
milkymist/dvisampler/datacapture.py
View File

@ -5,11 +5,10 @@ from migen.genlib.cdc import MultiReg, PulseSynchronizer
from migen.bank.description import * from migen.bank.description import *
class DataCapture(Module, AutoReg): class DataCapture(Module, AutoReg):
def __init__(self, ntbits): def __init__(self, ntbits, invert):
self.pad = Signal() self.pad = Signal()
self.serdesstrobe = Signal() self.serdesstrobe = Signal()
self.d0 = Signal() # pix5x clock domain self.d = Signal(10)
self.d1 = Signal() # pix5x clock domain
self._r_dly_ctl = RegisterRaw(4) self._r_dly_ctl = RegisterRaw(4)
self._r_dly_busy = RegisterField(1, READ_ONLY, WRITE_ONLY) self._r_dly_busy = RegisterField(1, READ_ONLY, WRITE_ONLY)
@ -42,7 +41,9 @@ class DataCapture(Module, AutoReg):
Instance.Input("T", 1) Instance.Input("T", 1)
) )
d0 = Signal()
d0p = Signal() d0p = Signal()
d1 = Signal()
d1p = Signal() d1p = Signal()
self.specials += Instance("ISERDES2", self.specials += Instance("ISERDES2",
Instance.Parameter("BITSLIP_ENABLE", "FALSE"), Instance.Parameter("BITSLIP_ENABLE", "FALSE"),
@ -50,9 +51,9 @@ class DataCapture(Module, AutoReg):
Instance.Parameter("DATA_WIDTH", 4), Instance.Parameter("DATA_WIDTH", 4),
Instance.Parameter("INTERFACE_TYPE", "RETIMED"), Instance.Parameter("INTERFACE_TYPE", "RETIMED"),
Instance.Parameter("SERDES_MODE", "NONE"), Instance.Parameter("SERDES_MODE", "NONE"),
Instance.Output("Q4", self.d0), Instance.Output("Q4", d0),
Instance.Output("Q3", d0p), Instance.Output("Q3", d0p),
Instance.Output("Q2", self.d1), Instance.Output("Q2", d1),
Instance.Output("Q1", d1p), Instance.Output("Q1", d1p),
Instance.Input("BITSLIP", 0), Instance.Input("BITSLIP", 0),
Instance.Input("CE0", 1), Instance.Input("CE0", 1),
@ -75,8 +76,8 @@ class DataCapture(Module, AutoReg):
self.sync.pix5x += [ self.sync.pix5x += [
If(reset_lateness, If(reset_lateness,
lateness.eq(2**(ntbits - 1)) lateness.eq(2**(ntbits - 1))
).Elif(~delay_busy & ~too_late & ~too_early & (self.d0 != self.d1), ).Elif(~delay_busy & ~too_late & ~too_early & (d0 != d1),
If(self.d0, If(d0,
# 1 -----> 0 # 1 -----> 0
# d0p # d0p
If(d0p, If(d0p,
@ -146,3 +147,14 @@ class DataCapture(Module, AutoReg):
reset_lateness.eq(self.do_reset_lateness.o), reset_lateness.eq(self.do_reset_lateness.o),
self.do_reset_lateness.i.eq(self._r_phase_reset.re) self.do_reset_lateness.i.eq(self._r_phase_reset.re)
] ]
# 2:10 deserialization
d0i = Signal()
d1i = Signal()
self.comb += [
d0i.eq(d0 ^ invert),
d1i.eq(d1 ^ invert)
]
dsr = Signal(10)
self.sync.pix5x += dsr.eq(Cat(dsr[2:], d0i, d1i))
self.sync.pix += self.d.eq(dsr)