examples/pytholite/uio: demonstrate memories
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@ -13,8 +13,12 @@ layout = [("r", BV(32))]
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def gen():
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ds = Register(32)
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for i in range(3):
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r = TRead(i, busname="mem")
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yield r
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ds.store = r.data
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yield Token("result", {"r": ds})
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for i in range(5):
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# NB: busname is optional when only one bus is configured
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r = TRead(i, busname="wb")
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yield r
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ds.store = r.data
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@ -46,20 +50,27 @@ def run_sim(ng):
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fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
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sim = Simulator(fragment, Runner())
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sim.run(30)
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sim.run(50)
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del sim
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def main():
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mem = Memory(32, 3, init=[42, 37, 81])
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dataflow = [("result", Source, layout)]
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buses = {
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"wb": wishbone.Interface(),
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"mem": mem
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}
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print("Simulating native Python:")
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ng_native = UnifiedIOSimulation(gen(),
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dataflow=[("result", Source, layout)],
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buses={"wb": wishbone.Interface()})
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dataflow=dataflow,
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buses=buses)
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run_sim(ng_native)
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print("Simulating Pytholite:")
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ng_pytholite = make_pytholite(gen,
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dataflow=[("result", Source, layout)],
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buses={"wb": wishbone.Interface()})
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dataflow=dataflow,
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buses=buses)
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run_sim(ng_pytholite)
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print("Converting Pytholite to Verilog:")
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