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examples/pytholite/uio: demonstrate memories

This commit is contained in:
Sebastien Bourdeauducq 2012-11-23 16:24:20 +01:00
parent f3efd74dfd
commit 7c6ebcf753
1 changed files with 17 additions and 6 deletions
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23
examples/pytholite/uio.py
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@ -13,8 +13,12 @@ layout = [("r", BV(32))]
def gen(): def gen():
ds = Register(32) ds = Register(32)
for i in range(3):
r = TRead(i, busname="mem")
yield r
ds.store = r.data
yield Token("result", {"r": ds})
for i in range(5): for i in range(5):
# NB: busname is optional when only one bus is configured
r = TRead(i, busname="wb") r = TRead(i, busname="wb")
yield r yield r
ds.store = r.data ds.store = r.data
@ -46,20 +50,27 @@ def run_sim(ng):
fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment() fragment = slave.get_fragment() + intercon.get_fragment() + c.get_fragment()
sim = Simulator(fragment, Runner()) sim = Simulator(fragment, Runner())
sim.run(30) sim.run(50)
del sim del sim
def main(): def main():
mem = Memory(32, 3, init=[42, 37, 81])
dataflow = [("result", Source, layout)]
buses = {
"wb": wishbone.Interface(),
"mem": mem
}
print("Simulating native Python:") print("Simulating native Python:")
ng_native = UnifiedIOSimulation(gen(), ng_native = UnifiedIOSimulation(gen(),
dataflow=[("result", Source, layout)], dataflow=dataflow,
buses={"wb": wishbone.Interface()}) buses=buses)
run_sim(ng_native) run_sim(ng_native)
print("Simulating Pytholite:") print("Simulating Pytholite:")
ng_pytholite = make_pytholite(gen, ng_pytholite = make_pytholite(gen,
dataflow=[("result", Source, layout)], dataflow=dataflow,
buses={"wb": wishbone.Interface()}) buses=buses)
run_sim(ng_pytholite) run_sim(ng_pytholite)
print("Converting Pytholite to Verilog:") print("Converting Pytholite to Verilog:")