Added US pritmives for Artix+
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@ -65,6 +65,8 @@ class XilinxPlatform(GenericPlatform):
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so.update(common.xilinx_s7_special_overrides)
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if self.device[:4] == "xcku":
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so.update(common.xilinx_us_special_overrides)
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if self.device[:4] == "xcau":
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so.update(common.xilinx_us_special_overrides)
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so.update(special_overrides)
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return GenericPlatform.get_verilog(self, *args,
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special_overrides = so,
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