litex_term: support Intel/Altera nios2-terminal
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parent
6f63fc104e
commit
7dae0aa09b
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@ -161,6 +161,33 @@ class JTAGUART:
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r = self.tcp.recv(1)
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os.write(self.file, bytes(r))
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# Intel/Altera JTAG UART via nios2-terminal
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class Nios2Terminal():
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def __init__(self):
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from subprocess import Popen, PIPE
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p = Popen("nios2-terminal", stdin=PIPE, stdout=PIPE)
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self.p = p
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def read(self):
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return self.p.stdout.read(1)
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def in_waiting(self):
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# unfortunately p.stdout does not provide
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# information about awaiting input
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return False
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def write(self, data):
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if data is not None:
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self.p.stdin.write(data)
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try:
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self.p.stdin.flush()
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except BrokenPipeError:
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print("nios2-terminal has terminated, exiting...\n")
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sys.exit(1)
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def close(self):
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self.p.terminate()
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# SFL ----------------------------------------------------------------------------------------------
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sfl_prompt_req = b"F7: boot from serial\n"
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@ -320,7 +347,7 @@ class LiteXTerm:
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def receive_upload_response(self):
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reply = self.port.read()
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if reply == sfl_ack_success:
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return
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return True
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elif reply == sfl_ack_crcerror:
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print("[LXTERM] Upload to device failed due to data corruption (CRC error)")
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else:
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@ -370,10 +397,12 @@ class LiteXTerm:
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# Inter-frame delay.
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time.sleep(self.delay)
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# Read response if availables.
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# Read response if available.
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while self.port.in_waiting:
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self.receive_upload_response()
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outstanding -= 1
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ack = self.receive_upload_response()
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if ack:
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outstanding -= 1
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break
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# Get remaining responses.
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for _ in range(outstanding):
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@ -418,7 +447,7 @@ class LiteXTerm:
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for filename, base in self.mem_regions.items():
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self.upload(filename, int(base, 16))
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self.boot()
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print("[LXTERM] Done.");
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print("[LXTERM] Done.")
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def reader(self):
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try:
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@ -493,7 +522,7 @@ class LiteXTerm:
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def _get_args():
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parser = argparse.ArgumentParser()
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parser.add_argument("port", help="Serial port")
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parser.add_argument("port", help="Serial port (eg /dev/tty*, crossover, jtag_uart, jtag_atlantic)")
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parser.add_argument("--speed", default=115200, help="Serial baudrate")
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parser.add_argument("--serial-boot", default=False, action='store_true', help="Automatically initiate serial boot")
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parser.add_argument("--kernel", default=None, help="Kernel image")
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@ -511,7 +540,12 @@ def main():
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raise NotImplementedError
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bridge_cls = {"crossover": CrossoverUART, "jtag_uart": JTAGUART}.get(args.port, None)
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bridge_kwargs = {"jtag_uart": {"config": args.jtag_config}}.get(args.port, {})
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if bridge_cls is not None:
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if args.port == "jtag_atlantic":
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term.port = Nios2Terminal()
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port = args.port
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term.payload_length = 128
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term.delay = 1e-6
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elif bridge_cls is not None:
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bridge = bridge_cls(**bridge_kwargs)
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bridge.open()
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port = os.ttyname(bridge.name)
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