targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
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@ -13,7 +13,10 @@ from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41K64M16
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from litedram.modules import MT41K64M16
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from litedram.phy import ECP5DDRPHY, ECP5DDRPHYInit
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from litedram.phy import ECP5DDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.core.mac import LiteEthMAC
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# CRG ----------------------------------------------------------------------------------------------
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# CRG ----------------------------------------------------------------------------------------------
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@ -70,7 +73,7 @@ class BaseSoC(SoCSDRAM):
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csr_map.update(SoCSDRAM.csr_map)
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csr_map.update(SoCSDRAM.csr_map)
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def __init__(self, toolchain="diamond", **kwargs):
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def __init__(self, toolchain="diamond", **kwargs):
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platform = versa_ecp5.Platform(toolchain=toolchain)
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platform = versa_ecp5.Platform(toolchain=toolchain)
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sys_clk_freq = int(50e6)
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sys_clk_freq = int(75e6)
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
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integrated_rom_size=0x8000,
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integrated_rom_size=0x8000,
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**kwargs)
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**kwargs)
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@ -84,24 +87,61 @@ class BaseSoC(SoCSDRAM):
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platform.request("ddram"),
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platform.request("ddram"),
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sys_clk_freq=sys_clk_freq)
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sys_clk_freq=sys_clk_freq)
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self.add_constant("ECP5DDRPHY", None)
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self.add_constant("ECP5DDRPHY", None)
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ddrphy_init = ECP5DDRPHYInit(self.crg, self.ddrphy)
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self.comb += crg.stop.eq(self.ddrphy.init.stop)
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self.submodules += ddrphy_init
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sdram_module = MT41K64M16(sys_clk_freq, "1:2")
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sdram_module = MT41K64M16(sys_clk_freq, "1:2")
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self.register_sdram(self.ddrphy,
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self.register_sdram(self.ddrphy,
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sdram_module.geom_settings,
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sdram_module.geom_settings,
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sdram_module.timing_settings)
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sdram_module.timing_settings)
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# EthernetSoC --------------------------------------------------------------------------------------
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class EthernetSoC(BaseSoC):
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csr_map = {
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"ethphy": 18,
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"ethmac": 19
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}
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csr_map.update(BaseSoC.csr_map)
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interrupt_map = {
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"ethmac": 3,
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}
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interrupt_map.update(BaseSoC.interrupt_map)
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mem_map = {
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"ethmac": 0x30000000, # (shadow @0xb0000000)
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}
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mem_map.update(BaseSoC.mem_map)
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def __init__(self, toolchain="diamond", **kwargs):
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BaseSoC.__init__(self, toolchain=toolchain, **kwargs)
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self.submodules.ethphy = LiteEthPHYRGMII(
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self.platform.request("eth_clocks"),
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self.platform.request("eth"))
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self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32,
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interface="wishbone", endianness=self.cpu.endianness)
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self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
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self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
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self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
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self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
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self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
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# Build --------------------------------------------------------------------------------------------
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# Build --------------------------------------------------------------------------------------------
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def main():
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on ECP5")
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parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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parser.add_argument("--gateware-toolchain", dest="toolchain", default="diamond",
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help='gateware toolchain to use, diamond (default) or trellis')
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help='gateware toolchain to use, diamond (default) or trellis')
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builder_args(parser)
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builder_args(parser)
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soc_sdram_args(parser)
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soc_sdram_args(parser)
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parser.add_argument("--with-ethernet", action="store_true",
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help="enable Ethernet support")
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args = parser.parse_args()
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args = parser.parse_args()
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soc = BaseSoC(toolchain=args.toolchain, **soc_sdram_argdict(args))
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cls = EthernetSoC if args.with_ethernet else BaseSoC
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soc = cls(args.toolchain, **soc_sdram_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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builder.build()
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