Remove Constant
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parent
79e5f24a65
commit
7e2bc00c0a
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@ -31,7 +31,7 @@ class _AddressSlicer:
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if isinstance(address, int):
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if isinstance(address, int):
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return (address & (2**self._b1 - 1)) << self.address_align
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return (address & (2**self._b1 - 1)) << self.address_align
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else:
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else:
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return Cat(Constant(0, BV(self.address_align)), address[:self._b1])
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return Cat(Replicate(0, self.address_align), address[:self._b1])
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class _Selector:
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class _Selector:
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def __init__(self, slicer, bankn, slots):
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def __init__(self, slicer, bankn, slots):
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@ -71,7 +71,7 @@ class _Steerer:
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sync = []
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sync = []
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def stb_and(cmd, attr):
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def stb_and(cmd, attr):
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if not hasattr(cmd, "stb"):
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if not hasattr(cmd, "stb"):
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return Constant(0)
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return 0
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else:
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else:
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return cmd.stb & getattr(cmd, attr)
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return cmd.stb & getattr(cmd, attr)
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for phase, sel in zip(self.dfi.phases, self.sel):
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for phase, sel in zip(self.dfi.phases, self.sel):
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@ -21,7 +21,7 @@ class UART:
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enable16 = Signal()
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enable16 = Signal()
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enable16_counter = Signal(BV(16))
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enable16_counter = Signal(BV(16))
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comb = [
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comb = [
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enable16.eq(enable16_counter == Constant(0, BV(16)))
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enable16.eq(enable16_counter == 0)
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]
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]
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sync = [
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sync = [
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enable16_counter.eq(enable16_counter - 1),
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enable16_counter.eq(enable16_counter - 1),
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@ -43,7 +43,7 @@ class UART:
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self.tx.eq(0)
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self.tx.eq(0)
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).Elif(enable16 & tx_busy,
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).Elif(enable16 & tx_busy,
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tx_count16.eq(tx_count16 + 1),
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tx_count16.eq(tx_count16 + 1),
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If(tx_count16 == Constant(0, BV(4)),
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If(tx_count16 == 0,
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tx_bitcount.eq(tx_bitcount + 1),
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tx_bitcount.eq(tx_bitcount + 1),
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If(tx_bitcount == 8,
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If(tx_bitcount == 8,
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self.tx.eq(1)
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self.tx.eq(1)
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13
top.py
13
top.py
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@ -97,14 +97,13 @@ def get():
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cpu0.ibus,
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cpu0.ibus,
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cpu0.dbus
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cpu0.dbus
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], [
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], [
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(binc("000"), norflash0.bus),
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(lambda a: a[26:29] == 0, norflash0.bus),
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(binc("001"), sram0.bus),
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(lambda a: a[26:29] == 1, sram0.bus),
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(binc("011"), minimac0.membus),
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(lambda a: a[26:29] == 3, minimac0.membus),
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(binc("10"), wishbone2asmi0.wishbone),
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(lambda a: a[27:29] == 2, wishbone2asmi0.wishbone),
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(binc("11"), wishbone2csr0.wishbone)
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(lambda a: a[27:29] == 3, wishbone2csr0.wishbone)
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],
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],
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register=True,
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register=True)
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offset=1)
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#
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#
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# CSR
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# CSR
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