Merge pull request #2007 from enjoy-digital/ctu-can-fd
Add initial CTU-CAN-FD core support.
This commit is contained in:
enjoy-digital
GitHub
commit
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#
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# CTU CAN-FD Core Wrapper for LiteX.
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#
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# Copyright (c) 2021 Andrew Dennison <andrew@motec.com.au>
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# Copyright (c) 2021-2024 Florent Kermarrec <florent@enjoy-digital.fr>
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# Copyright (c) 2024 Gwenhael Goavec-Merou <gwenhael@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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# Documentation at https://canbus.pages.fel.cvut.cz/
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import os
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import subprocess
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from migen import *
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from litex.gen import *
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from litex.build import tools
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from litex.build.vhd2v_converter import VHD2VConverter
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr_eventmanager import *
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# CTU CAN-FD ---------------------------------------------------------------------------------------
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class CTUCANFD(LiteXModule, EventManager):
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def __init__(self, platform, pads, timestamp=0, force_convert=False):
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# Parameters.
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self.platform = platform
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self.pads = pads
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self._force_convert = force_convert
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# Wishbone Bus.
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self.bus = wishbone.Interface(data_width=32)
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# CSRs.
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self.control = CSRStorage(32, fields=[
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CSRField("reset", size=1, values=[
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("``0b0``", "Normal Operation."),
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("``0b1`", "Hold the Core in Reset."),
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], reset=0b0),
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CSRField("reserved",size=31),
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])
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self.status = CSRStatus(32, fields=[
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CSRField("ready", size=1, values=[
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("``0b0``", "Core in Reset."),
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("``0b1`", "Core Ready."),
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]),
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])
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# IRQs.
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self.irq = Signal()
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# CTU CAN-FD Instance ----------------------------------------------------------------------
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self.core_params = dict()
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# Wishbone to CTU CAN-FD Memory Bus adaptation.
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self.mem_scs = mem_scs = Signal()
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self.mem_srd = mem_srd = Signal()
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self.mem_swr = mem_swr = Signal()
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self.mem_sbe = mem_sbe = Signal(4)
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self.mem_adress = mem_adress = Signal(16)
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self.mem_data_in = mem_data_in = Signal(32)
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self.mem_data_out = mem_data_out = Signal(32)
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self.comb += [
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# On Wishbone Access cycle...
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mem_scs.eq(self.bus.cyc & self.bus.stb),
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mem_srd.eq(mem_scs & ~self.bus.we & ~self.bus.ack),
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mem_swr.eq(mem_scs & self.bus.we),
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mem_sbe.eq(self.bus.sel),
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# Connect data_in/out.
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mem_data_in.eq(self.bus.dat_w),
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self.bus.dat_r.eq(mem_data_out),
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# Convert 32-bit word addressing to bytes addressing.
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mem_adress.eq(Cat(Signal(2), self.bus.adr)),
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]
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self.sync += [
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self.bus.ack.eq(0),
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If(mem_scs & ~self.bus.ack, self.bus.ack.eq(1)),
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]
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# CTU CAN-FD Parameters.
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self.core_params.update(
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# Target technology (ASIC or FPGA)
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#p_target_technology = C_TECH_FPGA
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# TX/RX Buffers.
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p_txt_buffer_count = 4, # Number of TX Buffers.
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p_rx_buffer_size = 32, # RX Buffer size (in 32-bit words).
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# Filter A-C.
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p_sup_filtA = False,
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p_sup_filtB = False,
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p_sup_filtC = False,
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# Range Filter.
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#p_sup_filtV = False,
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# Synthesize Range Filter
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p_sup_range = False,
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# Test registers.
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p_sup_test_registers = True, # True to have access to 0x9XX Tests registers
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# Traffic counters.
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p_sup_traffic_ctrs = False,
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# Add parity bit to TXT Buffer and RX Buffer RAMs
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p_sup_parity = False,
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# Number of active timestamp bits
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p_active_timestamp_bits = 63,
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# Reset TXT / RX Buffer RAMs
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p_reset_buffer_rams = False,
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)
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# CTU CAN-FD Signals.
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self.core_params.update(
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# Clk / Rst.
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i_clk_sys = ClockSignal("sys"),
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i_res_n = ~(ResetSignal("sys") | self.control.fields.reset),
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o_res_n_out = self.status.fields.ready,
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# DFT support (ASIC only).
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i_scan_enable = 0,
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# Timestamp (For time based transmission / reception).
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i_timestamp = timestamp,
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# Memory interface.
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i_scs = mem_scs,
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i_srd = mem_srd,
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i_swr = mem_swr,
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i_sbe = mem_sbe,
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i_adress = mem_adress,
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i_data_in = mem_data_in,
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o_data_out = mem_data_out,
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# Interrupt.
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o_int = self.irq,
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# CAN Bus.
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o_can_tx = pads.tx,
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i_can_rx = pads.rx,
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# Debug.
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#o_test_probe = ,
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)
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self.comb += pads.irq.eq(self.irq)
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def add_sources(self, platform):
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sources = []
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sdir = "CTU-CAN-FD"
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cdir = os.path.dirname(__file__)
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if not os.path.exists(sdir):
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os.system(f"git clone https://github.com/enjoy-digital/CTU-CAN-FD")
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with open(os.path.join(cdir, 'rtl_lst.txt')) as f:
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for line in f:
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srcfile = os.path.join(sdir, line.strip().replace('rtl', 'src'))
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self.vhd2v_converter.add_source(srcfile)
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def do_finalize(self):
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# CAN Core instance
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self.vhd2v_converter = VHD2VConverter(self.platform,
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top_entity = "can_top_level",
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build_dir = os.path.abspath(os.path.dirname(__file__)),
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work_package = "ctu_can_fd_rtl",
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force_convert = self._force_convert,
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params = self.core_params,
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add_instance = True,
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)
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# Add Sources.
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self.add_sources(self.platform)
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@ -0,0 +1,88 @@
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rtl/packages/unary_ops_pkg.vhd
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rtl/packages/can_fd_register_map.vhd
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rtl/packages/can_fd_frame_format.vhd
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rtl/packages/id_transfer_pkg.vhd
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rtl/packages/can_constants_pkg.vhd
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rtl/packages/can_config_pkg.vhd
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rtl/packages/can_types_pkg.vhd
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rtl/txt_buffer/txt_buffer_fsm.vhd
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rtl/tx_arbitrator/tx_arbitrator_fsm.vhd
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rtl/tx_arbitrator/priority_decoder.vhd
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rtl/tx_arbitrator/tx_arbitrator.vhd
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rtl/rx_buffer/rx_buffer_pointers.vhd
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rtl/rx_buffer/rx_buffer_fsm.vhd
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rtl/prescaler/trigger_generator.vhd
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rtl/prescaler/synchronisation_checker.vhd
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rtl/prescaler/segment_end_detector.vhd
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rtl/prescaler/bit_time_fsm.vhd
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rtl/prescaler/bit_time_counters.vhd
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rtl/prescaler/bit_time_cfg_capture.vhd
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rtl/prescaler/bit_segment_meter.vhd
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rtl/prescaler/prescaler.vhd
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rtl/memory_registers/generated/memory_reg_rw_lock.vhd
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rtl/memory_registers/generated/memory_reg_rw.vhd
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rtl/memory_registers/generated/memory_reg_os_lock.vhd
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rtl/memory_registers/generated/memory_reg_os.vhd
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rtl/memory_registers/generated/memory_bus.vhd
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rtl/memory_registers/generated/data_mux.vhd
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rtl/memory_registers/generated/cmn_reg_map_pkg.vhd
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rtl/memory_registers/generated/can_registers_pkg.vhd
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rtl/memory_registers/generated/test_registers_reg_map.vhd
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rtl/memory_registers/generated/control_registers_reg_map.vhd
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rtl/memory_registers/generated/address_decoder.vhd
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rtl/memory_registers/generated/access_signaler.vhd
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rtl/interrupt_manager/int_module.vhd
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rtl/interface/apb_ifc.vhd
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rtl/interface/ahb_ifc.vhd
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rtl/frame_filters/range_filter.vhd
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rtl/frame_filters/bit_filter.vhd
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rtl/frame_filters/frame_filters.vhd
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rtl/common_blocks/sig_sync.vhd
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rtl/common_blocks/shift_reg_preload.vhd
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rtl/common_blocks/shift_reg_byte.vhd
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rtl/common_blocks/shift_reg.vhd
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rtl/common_blocks/parity_calculator.vhd
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rtl/common_blocks/rst_sync.vhd
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rtl/common_blocks/rst_reg.vhd
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rtl/common_blocks/mux2.vhd
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rtl/common_blocks/majority_decoder_3.vhd
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rtl/common_blocks/inf_ram_wrapper.vhd
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rtl/txt_buffer/txt_buffer_ram.vhd
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rtl/rx_buffer/rx_buffer_ram.vhd
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rtl/common_blocks/endian_swapper.vhd
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rtl/common_blocks/dlc_decoder.vhd
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rtl/common_blocks/dff_arst_ce.vhd
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rtl/common_blocks/dff_arst.vhd
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rtl/interrupt_manager/int_manager.vhd
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rtl/common_blocks/clk_gate.vhd
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rtl/txt_buffer/txt_buffer.vhd
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rtl/rx_buffer/rx_buffer.vhd
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rtl/memory_registers/memory_registers.vhd
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rtl/can_core/tx_shift_reg.vhd
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rtl/can_core/trigger_mux.vhd
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rtl/can_core/rx_shift_reg.vhd
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rtl/can_core/retransmitt_counter.vhd
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rtl/can_core/reintegration_counter.vhd
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rtl/can_core/protocol_control_fsm.vhd
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rtl/can_core/operation_control.vhd
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rtl/can_core/fault_confinement_rules.vhd
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rtl/can_core/fault_confinement_fsm.vhd
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rtl/can_core/err_detector.vhd
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rtl/can_core/err_counters.vhd
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rtl/can_core/fault_confinement.vhd
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rtl/can_core/crc_calc.vhd
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rtl/can_core/control_counter.vhd
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rtl/can_core/protocol_control.vhd
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rtl/can_core/can_crc.vhd
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rtl/can_core/bus_traffic_counters.vhd
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rtl/can_core/bit_stuffing.vhd
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rtl/can_core/bit_destuffing.vhd
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rtl/can_core/can_core.vhd
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rtl/bus_sampling/tx_data_cache.vhd
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rtl/bus_sampling/trv_delay_meas.vhd
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rtl/bus_sampling/ssp_generator.vhd
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rtl/bus_sampling/sample_mux.vhd
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rtl/bus_sampling/data_edge_detector.vhd
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rtl/bus_sampling/bit_err_detector.vhd
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rtl/bus_sampling/bus_sampling.vhd
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rtl/can_top_level.vhd
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@ -633,6 +633,25 @@ def generate_dts(d, initrd_start=None, initrd_size=None, initrd=None, root_devic
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}};
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""".format(xadc_csr_base=d["csr_bases"]["xadc"])
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# CAN ------------------------------------------------------------------------------------------
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for mem in d["memories"]:
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if "can" in mem:
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dts += """
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{name}: can@{can_mem_base:x} {{
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compatible = "ctu,ctucanfd";
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reg = <0x{can_mem_base:x} 0x{can_mem_size:x}>;
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interrupt-parent = <&intc0>;
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interrupts = <{can_interrupt}>;
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clocks = <&sys_clk>;
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status = "okay";
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}};
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""".format(name=mem,
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can_mem_base=d["memories"][mem]["base"],
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can_mem_size=d["memories"][mem]["size"],
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can_interrupt = int(d["constants"][f"{mem}_interrupt"]),
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)
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# Framebuffer ----------------------------------------------------------------------------------
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if "video_framebuffer" in d["csr_bases"]:
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