soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient)
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@ -68,7 +68,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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cl = sdram_phy_settings.cl
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cl = sdram_phy_settings.cl
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if sdram_phy_settings.memtype == "SDR":
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if sdram_phy_settings.memtype == "SDR":
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bl = sdram_phy_settings.nphases
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bl = 1
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mr = log2_int(bl) + (cl << 4)
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mr = log2_int(bl) + (cl << 4)
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reset_dll = 1 << 8
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reset_dll = 1 << 8
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@ -83,7 +83,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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]
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]
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elif sdram_phy_settings.memtype == "DDR":
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elif sdram_phy_settings.memtype == "DDR":
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bl = 2*sdram_phy_settings.nphases
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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emr = 0
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reset_dll = 1 << 8
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reset_dll = 1 << 8
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@ -100,7 +100,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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]
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]
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elif sdram_phy_settings.memtype == "LPDDR":
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elif sdram_phy_settings.memtype == "LPDDR":
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bl = 2*sdram_phy_settings.nphases
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bl = 4
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mr = log2_int(bl) + (cl << 4)
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mr = log2_int(bl) + (cl << 4)
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emr = 0
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emr = 0
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reset_dll = 1 << 8
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reset_dll = 1 << 8
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@ -117,7 +117,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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]
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]
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elif sdram_phy_settings.memtype == "DDR2":
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elif sdram_phy_settings.memtype == "DDR2":
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bl = 2*sdram_phy_settings.nphases
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bl = 4
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wr = 2
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wr = 2
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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mr = log2_int(bl) + (cl << 4) + (wr << 9)
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emr = 0
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emr = 0
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@ -141,7 +141,7 @@ const unsigned int sdram_dfii_pix_rddata_addr[{n}] = {{
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("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
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("Load Extended Mode Register / OCD Exit", emr, 1, cmds["MODE_REGISTER"], 0),
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]
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]
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elif sdram_phy_settings.memtype == "DDR3":
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elif sdram_phy_settings.memtype == "DDR3":
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bl = 2*sdram_phy_settings.nphases
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bl = 8
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def format_mr0(bl, cl, wr, dll_reset):
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def format_mr0(bl, cl, wr, dll_reset):
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bl_to_mr0 = {
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bl_to_mr0 = {
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