soc/integration/cpu_interface: add bases, constants and memories output to csv files

This commit is contained in:
Florent Kermarrec 2015-11-14 22:04:33 +01:00
parent af909b43d5
commit 7ed2576ce1
3 changed files with 56 additions and 19 deletions

View File

@ -1,6 +1,6 @@
import csv
# TODO: share reg for all software drivers
# TODO: move
class MappedReg:
def __init__(self, readfn, writefn, name, addr, length, busword, mode):
@ -33,7 +33,7 @@ class MappedReg:
self.writefn(self.addr, datas)
class MappedRegs:
class MappedElements:
def __init__(self, d):
self.d = d
@ -42,15 +42,37 @@ class MappedRegs:
return self.__dict__['d'][attr]
except KeyError:
pass
raise KeyError("No such register " + attr)
raise KeyError("No such element " + attr)
def build_map(addrmap, busword, readfn, writefn):
def build_csr_bases(addrmap):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
name, addr, length, mode = item
addr = int(addr.replace("0x", ""), 16)
length = int(length)
d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
return MappedRegs(d)
group, name, addr, dummy0, dummy1 = item
if group == "csr_base":
d[name] = int(addr.replace("0x", ""), 16)
return MappedElements(d)
def build_csr_registers(addrmap, busword, readfn, writefn):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
group, name, addr, length, mode = item
if group == "csr_register":
addr = int(addr.replace("0x", ""), 16)
length = int(length)
d[name] = MappedReg(readfn, writefn, name, addr, length, busword, mode)
return MappedElements(d)
def build_constants(addrmap):
csv_reader = csv.reader(open(addrmap), delimiter=',', quotechar='#')
d = {}
for item in csv_reader:
group, name, value, dummy0, dummy1 = item
if group == "constant":
try:
d[name] = int(value)
except:
d[name] = value
return MappedElements(d)

View File

@ -1,8 +1,7 @@
import serial
from struct import *
# TODO: share reg for all software drivers
from litex.soc.cores.uart.software.reg import *
from litex.soc.cores.uart.software.csr import *
def write_b(uart, data):
@ -20,7 +19,9 @@ class UARTWishboneBridgeDriver:
self.debug = debug
self.uart = serial.Serial(port, baudrate, timeout=0.25)
if addrmap is not None:
self.regs = build_map(addrmap, busword, self.read, self.write)
self.bases = build_csr_bases(addrmap)
self.regs = build_csr_registers(addrmap, busword, self.read, self.write)
self.constants = build_constants(addrmap)
def open(self):
self.uart.flushOutput()

View File

@ -114,12 +114,26 @@ def get_csr_header(regions, constants, with_access_functions=True):
return r
def get_csr_csv(regions):
def get_csr_csv(csr_regions=None, constants=None, memory_regions=None):
r = ""
for name, origin, busword, obj in regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
if csr_regions is not None:
for name, origin, busword, obj in csr_regions:
r += "csr_base,{},0x{:08x},,\n".format(name, origin)
for name, origin, busword, obj in csr_regions:
if not isinstance(obj, Memory):
for csr in obj:
nr = (csr.size + busword - 1)//busword
r += "csr_register,{}_{},0x{:08x},{},{}\n".format(name, csr.name, origin, nr, "ro" if isinstance(csr, CSRStatus) else "rw")
origin += 4*nr
if constants is not None:
for name, value in constants:
r += "constant,{},{},,\n".format(name.lower(), value)
if memory_regions is not None:
for name, origin, length in memory_regions:
r += "memory_region,{},0x{:08x},{:d},\n".format(name.lower(), origin, length)
return r