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soc/add_ethernet: Review/Minor changes to TXSlots write-only mode.

This commit is contained in:
Florent Kermarrec 2023-07-03 10:50:47 +02:00
parent 646c917d7f
commit 7fa7a4c72a
1 changed files with 4 additions and 6 deletions
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10
litex/soc/integration/soc.py
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@ -1644,9 +1644,8 @@ class LiteXSoC(SoC):
# Add Ethernet ---------------------------------------------------------------------------------
def add_ethernet(self, name="ethmac", phy=None, phy_cd="eth", dynamic_ip=False, software_debug=False,
data_width = 8,
nrxslots = 2,
ntxslots = 2,
tx_write_only = False,
nrxslots = 2, rxslots_read_only = True,
ntxslots = 2, txslots_write_only = False,
with_timestamp = False,
with_timing_constraints = True):
# Imports
@ -1664,9 +1663,8 @@ class LiteXSoC(SoC):
dw = 32,
interface = "wishbone",
endianness = self.cpu.endianness,
nrxslots = nrxslots,
ntxslots = ntxslots,
tx_write_only = tx_write_only,
nrxslots = nrxslots, rxslots_read_only = rxslots_read_only,
ntxslots = ntxslots, txslots_write_only = txslots_write_only,
timestamp = None if not with_timestamp else self.timer0.uptime_cycles,
with_preamble_crc = not software_debug,
with_sys_datapath = with_sys_datapath)