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sdram/module: clean up tREFI. (use 64ms/8k or 4k)

This commit is contained in:
Florent Kermarrec 2015-03-28 01:09:21 +01:00
parent 54a88da5b8
commit 7fe748e1b0
1 changed files with 3 additions and 4 deletions
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7
misoclib/mem/sdram/module.py
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@ -13,7 +13,6 @@
# configurations. # configurations.
# - Modules can have different speedgrades, add support for it (and also add # - Modules can have different speedgrades, add support for it (and also add
# a check to verify clk_freq is in the supported range) # a check to verify clk_freq is in the supported range)
# Try to uniformize tREFI computations between modules
from math import ceil from math import ceil
@ -57,7 +56,7 @@ class IS42S16160(SDRAMModule):
"tRCD": 20, "tRCD": 20,
"tWR": 20, "tWR": 20,
"tWTR": 2, "tWTR": 2,
"tREFI": 7800, "tREFI": 64*1000*1000/8192,
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
@ -94,7 +93,7 @@ class AS4C16M16(SDRAMModule):
"tRCD": 18, "tRCD": 18,
"tWR": 12, "tWR": 12,
"tWTR": 2, "tWTR": 2,
"tREFI": 7800, "tREFI": 64*1000*1000/8192,
"tRFC": 60 "tRFC": 60
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):
@ -113,7 +112,7 @@ class MT46V32M16(SDRAMModule):
"tRCD": 15, "tRCD": 15,
"tWR": 15, "tWR": 15,
"tWTR": 2, "tWTR": 2,
"tREFI": 7800, "tREFI": 64*1000*1000/8192,
"tRFC": 70 "tRFC": 70
} }
def __init__(self, clk_freq): def __init__(self, clk_freq):