memtest/LFSR: test bench
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@ -13,7 +13,7 @@ class LFSR(Module):
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curval = [state[i] for i in range(n_state)]
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curval += [0]*(n_out - n_state)
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for i in range(n_out):
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nv = optree("^", [curval[tap] for tap in taps])
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nv = ~optree("^", [curval[tap] for tap in taps])
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curval.insert(0, nv)
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curval.pop()
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@ -22,9 +22,24 @@ class LFSR(Module):
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self.o.eq(Cat(*curval))
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)
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def _printcode():
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def _print_lfsr_code():
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dut = LFSR(3, 4, [3, 2])
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print(verilog.convert(dut, ios={dut.ce, dut.o}))
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class _LFSRTB(Module):
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def __init__(self, *args, **kwargs):
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self.submodules.lfsr = LFSR(*args, **kwargs)
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self.comb += self.lfsr.ce.eq(1)
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def do_simulation(self, s):
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print(s.rd(self.lfsr.o))
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def _sim_lfsr():
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from migen.sim.generic import Simulator
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tb = _LFSRTB(3, 4, [3, 2])
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sim = Simulator(tb)
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sim.run(20)
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if __name__ == "__main__":
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_printcode()
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_print_lfsr_code()
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_sim_lfsr()
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