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bus/asmibus: fix per-port tag generation

This commit is contained in:
Sebastien Bourdeauducq 2012-07-12 19:37:50 +02:00
parent c543edf6f3
commit 8062e48697
1 changed files with 4 additions and 2 deletions
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6
migen/bus/asmibus.py
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@ -101,9 +101,11 @@ class Port:
s.allocate_adr.eq(self.adr) s.allocate_adr.eq(self.adr)
] ]
choose_slot = None choose_slot = None
for s in reversed(self.slots): needs_tags = len(self.slots) > 1
for n, s in reversed(list(enumerate(self.slots))):
choose_slot = If(s.state == SLOT_EMPTY, choose_slot = If(s.state == SLOT_EMPTY,
s.allocate.eq(self.stb) s.allocate.eq(self.stb),
self.tag_issue.eq(n) if needs_tags else None
).Else(choose_slot) ).Else(choose_slot)
comb.append(choose_slot) comb.append(choose_slot)
comb.append(self.ack.eq(optree("|", comb.append(self.ack.eq(optree("|",