Add sigma-delta DAC LiteX core.
Signed-off-by: Tim Callahan <tcal@google.com>
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Tim Callahan <tcal@google.com>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.soc.interconnect.csr import *
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# DAC ---------------------------------------------------------------------------------------
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class DAC(Module, AutoCSR):
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def __init__(self, out, data_width):
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self.out = out
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self._value = CSRStorage(data_width, reset_less=True, description="Digital value to convert to analog.")
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value = Signal(data_width)
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accum = Signal(data_width+1)
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self.comb += value.eq(self._value.storage)
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self.sync += accum.eq(accum[0:data_width] + value)
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self.comb += out.eq(accum[data_width])
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