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soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter

This commit is contained in:
Florent Kermarrec 2019-09-28 12:35:41 +02:00
parent 7660dc22e1
commit 8099b0beb6
8 changed files with 57 additions and 18 deletions
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12
litex/soc/cores/cpu/lm32/core.py
View File

@ -44,7 +44,7 @@ class LM32(Module):
def reserved_interrupts(self):
return {}
def __init__(self, platform, eba_reset, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -58,8 +58,6 @@ class LM32(Module):
i_adr_o = Signal(32)
d_adr_o = Signal(32)
self.cpu_params = dict(
p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(eba_reset)),
i_clk_i=ClockSignal(),
i_rst_i=ResetSignal() | self.reset,
@ -99,6 +97,13 @@ class LM32(Module):
# add verilog sources
self.add_sources(platform, variant)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(
p_eba_reset=Instance.PreformattedParam("32'h{:08x}".format(reset_address))
)
@staticmethod
def add_sources(platform, variant):
vdir = os.path.join(
@ -133,4 +138,5 @@ class LM32(Module):
raise TypeError("Unknown variant {}".format(variant))
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("lm32_cpu", **self.cpu_params)

8
litex/soc/cores/cpu/minerva/core.py
View File

@ -39,7 +39,7 @@ class Minerva(Module):
def reserved_interrupts(self):
return {}
def __init__(self, platform, cpu_reset_address, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant is "standard", "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -88,6 +88,11 @@ class Minerva(Module):
# add verilog sources
self.add_sources(platform)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
assert reset_address == 0x00000000, "cpu_reset_addr hardcoded during elaboration!"
@staticmethod
def add_sources(platform):
vdir = os.path.join(
@ -95,4 +100,5 @@ class Minerva(Module):
platform.add_source(os.path.join(vdir, "minerva.v"))
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("minerva_cpu", **self.cpu_params)

9
litex/soc/cores/cpu/mor1kx/core.py
View File

@ -58,7 +58,7 @@ class MOR1KX(Module):
def reserved_interrupts(self):
return {"nmi": 0}
def __init__(self, platform, reset_pc, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -90,7 +90,6 @@ class MOR1KX(Module):
p_FEATURE_CMOV="ENABLED",
p_FEATURE_FFL1="ENABLED",
p_OPTION_CPU0="CAPPUCCINO",
p_OPTION_RESET_PC=reset_pc,
p_IBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
p_DBUS_WB_TYPE="B3_REGISTERED_FEEDBACK",
)
@ -157,6 +156,11 @@ class MOR1KX(Module):
# add verilog sources
self.add_sources(platform)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(p_OPTION_RESET_PC=reset_address)
@staticmethod
def add_sources(platform):
vdir = os.path.join(
@ -166,4 +170,5 @@ class MOR1KX(Module):
platform.add_verilog_include_path(vdir)
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("mor1kx", **self.cpu_params)

13
litex/soc/cores/cpu/picorv32/core.py
View File

@ -61,7 +61,7 @@ class PicoRV32(Module):
"bus_error": 2
}
def __init__(self, platform, progaddr_reset, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -106,8 +106,6 @@ class PicoRV32(Module):
p_ENABLE_TRACE=0,
p_MASKED_IRQ=0x00000000,
p_LATCHED_IRQ=0xffffffff,
p_PROGADDR_RESET=progaddr_reset,
p_PROGADDR_IRQ=progaddr_reset + 0x00000010,
p_STACKADDR=0xffffffff
)
@ -195,6 +193,14 @@ class PicoRV32(Module):
# add verilog sources
self.add_sources(platform)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(
p_PROGADDR_RESET=reset_address,
p_PROGADDR_IRQ=reset_address + 0x00000010
)
@staticmethod
def add_sources(platform):
vdir = os.path.join(
@ -202,4 +208,5 @@ class PicoRV32(Module):
platform.add_source(os.path.join(vdir, "picorv32.v"))
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("picorv32", **self.cpu_params)

10
litex/soc/cores/cpu/rocket/core.py
View File

@ -76,9 +76,9 @@ class RocketRV64(Module):
def reserved_interrupts(self):
return {}
def __init__(self, platform, cpu_reset_addr, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
assert cpu_reset_addr == 0x10000000, "cpu_reset_addr hardcoded in Chisel elaboration!"
self.platform = platform
self.variant = variant
@ -231,6 +231,11 @@ class RocketRV64(Module):
# add verilog sources
self.add_sources(platform, variant)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
assert reset_address == 0x10000000, "cpu_reset_addr hardcoded in during elaboration!"
@staticmethod
def add_sources(platform, variant="standard"):
vdir = os.path.join(
@ -248,4 +253,5 @@ class RocketRV64(Module):
)
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("ExampleRocketSystem", **self.cpu_params)

10
litex/soc/cores/cpu/serv/core.py
View File

@ -39,7 +39,7 @@ class SERV(Module):
def reserved_interrupts(self):
return {}
def __init__(self, platform, cpu_reset_address, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant is "standard", "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -51,8 +51,6 @@ class SERV(Module):
# # #
self.cpu_params -= dict(
p_RESET_PC=cpu_reset_address,
# clock / reset
i_clk = ClockSignal(),
i_i_rst = ResetSignal(),
@ -84,6 +82,11 @@ class SERV(Module):
# add verilog sources
self.add_sources(platform)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(p_RESET_PC=reset_address)
@staticmethod
def add_sources(platform):
vdir = os.path.join(
@ -93,4 +96,5 @@ class SERV(Module):
platform.add_verilog_include_path(vdir)
def do_finalize(self):
assert hasattr(self, "reset_address")
self.specials += Instance("serv_top", **self.cpu_params)

10
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -100,7 +100,7 @@ class VexRiscv(Module, AutoCSR):
def reserved_interrupts(self):
return {}
def __init__(self, platform, cpu_reset_address, variant="standard"):
def __init__(self, platform, variant="standard"):
assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
self.platform = platform
self.variant = variant
@ -108,7 +108,6 @@ class VexRiscv(Module, AutoCSR):
self.reset = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.cpu_reset_address = cpu_reset_address
self.interrupt = Signal(32)
@ -116,7 +115,6 @@ class VexRiscv(Module, AutoCSR):
i_clk=ClockSignal(),
i_reset=ResetSignal() | self.reset,
i_externalResetVector=self.cpu_reset_address,
i_externalInterruptArray=self.interrupt,
i_timerInterrupt=0,
i_softwareInterrupt=0,
@ -237,6 +235,11 @@ class VexRiscv(Module, AutoCSR):
o_debug_resetOut=self.o_resetOut
)
def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(i_externalResetVector=reset_address)
def add_timer(self):
self.submodules.timer = VexRiscvTimer()
self.cpu_params.update(i_timerInterrupt=self.timer.interrupt)
@ -252,6 +255,7 @@ class VexRiscv(Module, AutoCSR):
self.platform.add_source(variant_filename)
def do_finalize(self):
assert hasattr(self, "reset_address")
if not self.external_variant:
self.add_sources(self.platform, self.variant)
self.specials += Instance("VexRiscv", **self.cpu_params)

3
litex/soc/integration/soc_core.py
View File

@ -266,7 +266,8 @@ class SoCCore(Module):
# CPU selection / instance
if cpu_type not in cpu.CPUS.keys():
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_reset_address, self.cpu_variant))
self.add_cpu(cpu.CPUS[cpu_type](platform, self.cpu_variant))
self.cpu.set_reset_address(cpu_reset_address)
# Add Instruction/Data buses as Wisbone masters
self.add_wb_master(self.cpu.ibus)