Merge pull request #1258 from antmicro/4_bit_dqs
Make memtest work with 4x DQ / DQS ratio
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commit
80b309d1a4
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@ -346,9 +346,19 @@ static unsigned int sdram_write_read_check_test_pattern(int module, unsigned int
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/* Verify bytes matching current 'module' */
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/* Verify bytes matching current 'module' */
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for (int i = 0; i < DFII_PIX_DATA_BYTES; ++i) {
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for (int i = 0; i < DFII_PIX_DATA_BYTES; ++i) {
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int j = p * DFII_PIX_DATA_BYTES + i;
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int j = p * DFII_PIX_DATA_BYTES + i;
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#if SDRAM_PHY_DQ_DQS_RATIO == 4
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if (j % (SDRAM_PHY_MODULES/2) == ((SDRAM_PHY_MODULES-1)/2)-(module/2)) {
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if(module % 2) {
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errors += popcount((prs[p][i] & 0xf0) ^ (tst[i] & 0xf0));
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} else {
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errors += popcount((prs[p][i] & 0x0f) ^ (tst[i] & 0x0f));
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}
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}
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#else
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if (j % SDRAM_PHY_MODULES == SDRAM_PHY_MODULES-1-module) {
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if (j % SDRAM_PHY_MODULES == SDRAM_PHY_MODULES-1-module) {
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errors += popcount(prs[p][i] ^ tst[i]);
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errors += popcount(prs[p][i] ^ tst[i]);
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}
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}
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#endif
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}
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}
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}
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}
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@ -636,7 +646,11 @@ static int sdram_write_leveling_scan(int *delays, int loops, int show)
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ddrphy_wlevel_strobe_write(1);
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ddrphy_wlevel_strobe_write(1);
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cdelay(100);
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cdelay(100);
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csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr(0), buf, DFII_PIX_DATA_BYTES);
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csr_rd_buf_uint8(sdram_dfii_pix_rddata_addr(0), buf, DFII_PIX_DATA_BYTES);
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#if SDRAM_PHY_DQ_DQS_RATIO == 4
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if (buf[SDRAM_PHY_MODULES-1-(i/2)] != 0)
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#else
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if (buf[SDRAM_PHY_MODULES-1-i] != 0)
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if (buf[SDRAM_PHY_MODULES-1-i] != 0)
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#endif
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one_count++;
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one_count++;
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else
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else
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zero_count++;
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zero_count++;
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