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build/sim/verilator: add trace parameter to enable tracer

This commit is contained in:
Florent Kermarrec 2018-11-20 18:49:01 +01:00
parent 7359a99bf9
commit 80bdae0e55
2 changed files with 40 additions and 26 deletions
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5
litex/build/sim/core/sim.c
View File

@ -22,6 +22,7 @@
#include <event2/event.h> #include <event2/event.h>
void litex_sim_init(void **out); void litex_sim_init(void **out);
void litex_sim_dump();
struct session_list_s { struct session_list_s {
void *session; void *session;
@ -175,7 +176,6 @@ static void cb(int sock, short which, void *arg)
int i; int i;
//litex_sim_eval(vdut);
for(i = 0; i < 1000; i++) for(i = 0; i < 1000; i++)
{ {
for(s = sesslist; s; s=s->next) for(s = sesslist; s; s=s->next)
@ -184,14 +184,13 @@ static void cb(int sock, short which, void *arg)
s->module->tick(s->session); s->module->tick(s->session);
} }
litex_sim_eval(vdut); litex_sim_eval(vdut);
litex_sim_dump();
for(s = sesslist; s; s=s->next) for(s = sesslist; s; s=s->next)
{ {
if(!s->tickfirst) if(!s->tickfirst)
s->module->tick(s->session); s->module->tick(s->session);
} }
} }
//litex_sim_eval(vdut);
if (!evtimer_pending(ev, NULL)) { if (!evtimer_pending(ev, NULL)) {
event_del(ev); event_del(ev);

21
litex/build/sim/verilator.py
View File

@ -60,7 +60,7 @@ def _generate_sim_cpp_struct(name, index, siglist):
return content return content
def _generate_sim_cpp(platform): def _generate_sim_cpp(platform, trace=False):
content = """\ content = """\
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
@ -69,12 +69,27 @@ def _generate_sim_cpp(platform):
#include <verilated.h> #include <verilated.h>
#include "dut_header.h" #include "dut_header.h"
extern "C" void litex_sim_init_tracer(void *vdut);
extern "C" void litex_sim_tracer_dump();
extern "C" void litex_sim_dump()
{
"""
if trace:
content += """\
litex_sim_tracer_dump();
"""
content += """\
}
extern "C" void litex_sim_init(void **out) extern "C" void litex_sim_init(void **out)
{ {
Vdut *dut; Vdut *dut;
dut = new Vdut; dut = new Vdut;
litex_sim_init_tracer(dut);
""" """
for args in platform.sim_requested: for args in platform.sim_requested:
content += _generate_sim_cpp_struct(*args) content += _generate_sim_cpp_struct(*args)
@ -146,7 +161,7 @@ def _run_sim(build_name, as_root=False):
class SimVerilatorToolchain: class SimVerilatorToolchain:
def build(self, platform, fragment, build_dir="build", build_name="dut", def build(self, platform, fragment, build_dir="build", build_name="dut",
toolchain_path=None, serial="console", build=True, run=True, threads=1, toolchain_path=None, serial="console", build=True, run=True, threads=1,
verbose=True, sim_config=None): verbose=True, sim_config=None, trace=False):
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir) os.chdir(build_dir)
@ -168,7 +183,7 @@ class SimVerilatorToolchain:
include_paths.append(path) include_paths.append(path)
include_paths += platform.verilog_include_paths include_paths += platform.verilog_include_paths
_generate_sim_h(platform) _generate_sim_h(platform)
_generate_sim_cpp(platform) _generate_sim_cpp(platform, trace)
_generate_sim_variables(include_paths) _generate_sim_variables(include_paths)
if sim_config: if sim_config:
_generate_sim_config(sim_config) _generate_sim_config(sim_config)