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soc/integration/soc_sdram: always generate L2_SIZE constant

This commit is contained in:
Florent Kermarrec 2016-04-27 12:34:18 +02:00
parent 4e451a78d6
commit 80d673e502
1 changed files with 1 additions and 2 deletions
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3
litex/soc/integration/soc_sdram.py
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@ -68,8 +68,7 @@ class SoCSDRAM(SoCCore):
geom_settings.colbits)*sdram_width//8 geom_settings.colbits)*sdram_width//8
# XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories. # XXX: Limit main_ram_size to 256MB, we should modify mem_map to allow larger memories.
main_ram_size = min(main_ram_size, 256*1024*1024) main_ram_size = min(main_ram_size, 256*1024*1024)
if self.l2_size: self.add_constant("L2_SIZE", self.l2_size)
self.add_constant("L2_SIZE", self.l2_size)
# add a Wishbone interface to the DRAM # add a Wishbone interface to the DRAM
wb_sdram = wishbone.Interface() wb_sdram = wishbone.Interface()