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interconnect/ahb/AHB2Wishbone: Simplify and add proper Address/Data-Phases.

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This commit is contained in:
Florent Kermarrec 2024-01-10 12:10:15 +01:00
parent a2c2d70841
commit 80dfb5ca34
1 changed files with 10 additions and 13 deletions
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19
litex/soc/interconnect/ahb.py
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@ -66,27 +66,24 @@ class AHB2Wishbone(LiteXModule):
# FSM. # FSM.
self.fsm = fsm = FSM() self.fsm = fsm = FSM()
fsm.act("IDLE", fsm.act("ADDRESS-PHASE",
ahb.readyout.eq(1), ahb.readyout.eq(1),
If(ahb.sel & If(ahb.sel &
(ahb.size <= log2_int(ahb.data_width//8)) & (ahb.size <= log2_int(ahb.data_width//8)) &
(ahb.trans == AHBTransferType.NONSEQUENTIAL), (ahb.trans == AHBTransferType.NONSEQUENTIAL),
NextValue(wishbone.adr, ahb.addr[wishbone_adr_shift:]), NextValue(wishbone.adr, ahb.addr[wishbone_adr_shift:]),
NextValue(wishbone.dat_w, ahb.wdata),
NextValue(wishbone.we, ahb.write), NextValue(wishbone.we, ahb.write),
NextValue(wishbone.sel, 2**len(wishbone.sel) - 1), NextState("DATA-PHASE"),
NextState("ACT"),
) )
) )
fsm.act("ACT", fsm.act("DATA-PHASE",
wishbone.stb.eq(1), wishbone.stb.eq(1),
wishbone.cyc.eq(1), wishbone.cyc.eq(1),
wishbone.dat_w.eq(ahb.wdata),
wishbone.sel.eq(2**len(wishbone.sel) - 1),
ahb.resp.eq(wishbone.err),
If(wishbone.ack, If(wishbone.ack,
If(~wishbone.we, NextValue(ahb.rdata, wishbone.dat_r),
NextValue(ahb.rdata, wishbone.dat_r) NextState("ADDRESS-PHASE")
),
NextState("IDLE")
) )
) )
self.comb += ahb.resp.eq(wishbone.err)