use mibuild for de1 example
This commit is contained in:
Florent Kermarrec
parent
58a6acba27
commit
80e9db7e61
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@ -1,29 +1,14 @@
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PYTHON=c:\Python32\python
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PYTHON=C:\Python32\python
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all: build/de1.sta
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# We need to change to the build directory because the Quartus tools
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# tend to dump a mess of various files in the current directory.
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all: build/top.sta
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build/de1.qsf:
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build/top.sta:
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cp top.sdc build/top.sdc
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$(PYTHON) build.py
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build/de1.map: build/de1.qsf
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cp de1.qpf build/de1.qpf
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cp de1.sdc build/de1.sdc
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cd build && quartus_map de1.qpf
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build/de1.fit: build/de1.map
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cd build && quartus_fit de1.qpf
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build/de1.asm: build/de1.fit
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cd build && quartus_asm de1.qpf
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build/de1.sta: build/de1.asm
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cd build && quartus_sta de1.qpf
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load:
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cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;de1.sof"
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cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
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clean:
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rm -rf build/*
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@ -1,36 +1,34 @@
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import os
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from mibuild.platforms import de1
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from mibuild.altera_quartus import _add_period_constraint
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import top
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# list Verilog sources before changing directory
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verilog_sources = []
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def add_core_dir(d):
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root = os.path.join("verilog", d, "rtl")
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files = os.listdir(root)
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for f in files:
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if f[-2:] == ".v":
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verilog_sources.append(os.path.join(root, f))
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def add_core_files(d, files):
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for f in files:
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verilog_sources.append(os.path.join("verilog", d, f))
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def main():
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plat = de1.Platform()
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soc = top.SoC()
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# set pin constraints
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plat.request("clk50", obj=soc.clk50)
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plat.request("key", obj=soc.key)
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plat.request("ledg", obj=soc.led)
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plat.request("gpio_0", obj=soc.gpio_0)
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# set extra constraints
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plat.add_platform_command("""
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name TOP_LEVEL_ENTITY "top"
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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""")
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def get_qsf_prj():
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r = ""
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for s in verilog_sources:
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r += "set_global_assignment -name VERILOG_FILE " + s + "\n"
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return r
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_add_period_constraint(plat, "sys_clk", 20.0)
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cd = dict()
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cd["sys"] = soc.cd_sys
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plat.build_cmdline(soc.get_fragment(), clock_domains=cd)
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os.chdir("build")
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def str2file(filename, contents):
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f = open(filename, "w")
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f.write(contents)
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f.close()
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# generate top
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(src_verilog, qsf_cst) = top.get()
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str2file("de1.v", src_verilog)
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verilog_sources.append("build/de1.v")
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# generate Quartus project file
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qsf_prj = get_qsf_prj()
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str2file("de1.qsf", qsf_prj + qsf_cst)
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if __name__ == "__main__":
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main()
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@ -1,62 +0,0 @@
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class Constraints:
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def __init__(self, in_rst_n, cd_in, spi2csr0, led0, sw0):
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self.constraints = []
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def add(signal, pin, vec=-1, iostandard="3.3-V LVTTL", extra="", sch=""):
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self.constraints.append((signal, vec, pin, iostandard, extra,sch))
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def add_vec(signal, pins, iostandard="3.3-V LVTTL", extra="", sch=""):
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assert(signal.nbits == len(pins)), "%s size : %d / qsf size : %d" %(signal,signal.bv.width,len(pins))
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i = 0
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for p in pins:
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add(signal, p, i, iostandard, extra)
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i += 1
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# sys_clk
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add(cd_in.clk, "L1") # CLOCK_50
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# sys_rst
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add(in_rst_n, "R22") # KEY[0]
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# spi2csr0
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add(spi2csr0.spi_clk, "F13") #GPIO_1[9]
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add(spi2csr0.spi_cs_n, "G15") #GPIO_1[3]
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add(spi2csr0.spi_mosi, "E15") #GPIO_1[5]
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add(spi2csr0.spi_miso, "G16") #GPIO_1[7]
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# led0
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add_vec(led0, ["U22", "U21", "V22", "V21",
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"W22" , "W21" , "Y22" , "Y21"])
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# sw0
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add_vec(sw0, ["L22", "L21", "M22", "V12",
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"W12" , "U12" , "U11" , "M2"])
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def get_ios(self):
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return set([c[0] for c in self.constraints])
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def get_qsf(self, ns):
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r = ""
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for c in self.constraints:
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r += "set_location_assignment PIN_"+str(c[2])
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r += " -to " + ns.get_name(c[0])
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if c[1] >= 0:
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r += "[" + str(c[1]) + "]"
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r += "\n"
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r += "set_instance_assignment -name IO_STANDARD "
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r += "\"" + c[3] + "\""
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r += " -to " + ns.get_name(c[0])
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if c[1] >= 0:
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r += "[" + str(c[1]) + "]"
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r += "\n"
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r += """
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set_global_assignment -name FAMILY "Cyclone II"
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set_global_assignment -name DEVICE EP2C20F484C7
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set_global_assignment -name TOP_LEVEL_ENTITY "de1"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name DUTY_CYCLE 50 -section_id in_clk
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set_global_assignment -name FMAX_REQUIREMENT "50.0 MHz" -section_id in_clk
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"""
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return r
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@ -1,3 +0,0 @@
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# Revisions
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PROJECT_REVISION = "de1"
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@ -1,4 +0,0 @@
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#
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# Clocks
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#
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create_clock -period 50MHz [get_ports in_clk]
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@ -43,7 +43,6 @@ from miscope import trigger, recorder, miio, mila
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from miscope.bridges import spi2csr
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from timings import *
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from constraints import Constraints
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from math import sin
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@ -74,128 +73,128 @@ MILA1_ADDR = 0x0600
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#==============================================================================
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# M I S C O P E E X A M P L E
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#==============================================================================
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def get():
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class SoC:
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def __init__(self):
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# migIo0
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self.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
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# migLa0
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self.term0 = trigger.Term(trig0_width)
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self.trigger0 = trigger.Trigger(trig0_width, [self.term0])
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self.recorder0 = recorder.Recorder(dat0_width, record_size)
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self.miLa0 = mila.MiLa(MILA0_ADDR, self.trigger0, self.recorder0)
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# migLa1
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self.term1 = trigger.Term(trig1_width)
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self.trigger1 = trigger.Trigger(trig1_width, [self.term1])
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self.recorder1 = recorder.Recorder(dat1_width, record_size)
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self.miLa1 = mila.MiLa(MILA1_ADDR, self.trigger1, self.recorder1)
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# Spi2Csr
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self.spi2csr0 = spi2csr.Spi2Csr(16,8)
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# Csr Interconnect
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self.csrcon0 = csr.Interconnect(self.spi2csr0.csr,
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[
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self.miIo0.bank.bus,
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self.miLa0.trigger.bank.bus,
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self.miLa0.recorder.bank.bus,
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self.miLa1.trigger.bank.bus,
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self.miLa1.recorder.bank.bus
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])
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self.clk50 = Signal()
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self.led = Signal(8)
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self.gpio_0 = Signal(36)
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self.key = Signal(4)
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self.cd_sys = ClockDomain("sys")
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def get_fragment(self):
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comb = []
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sync = []
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#
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# Signal Generator
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#
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# Counter
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cnt_gen = Signal(8)
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sync += [
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cnt_gen.eq(cnt_gen+1)
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]
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# Square
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square_gen = Signal(8)
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sync += [
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If(cnt_gen[7],
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square_gen.eq(255)
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).Else(
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square_gen.eq(0)
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)
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]
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus_re = Signal()
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sinus_gen = Signal(8)
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comb +=[sinus_re.eq(1)]
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sinus_mem = Memory(8, 256, init = sinus)
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sinus_port = sinus_mem.get_port(has_re=True)
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comb += [
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sinus_port.adr.eq(cnt_gen),
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sinus_port.re.eq(sinus_re),
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sinus_gen.eq(sinus_port.dat_r)
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]
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# Signal Selection
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sig_gen = Signal(8)
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comb += [
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If(self.miIo0.o == 0,
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sig_gen.eq(cnt_gen)
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).Elif(self.miIo0.o == 1,
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sig_gen.eq(square_gen)
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).Elif(self.miIo0.o == 2,
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sig_gen.eq(sinus_gen)
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).Else(
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sig_gen.eq(0)
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)
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]
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# Led
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comb += [self.led.eq(self.miIo0.o[:8])]
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# MigLa0 input
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comb += [
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self.miLa0.trig.eq(sig_gen),
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self.miLa0.dat.eq(sig_gen)
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]
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# MigLa1 input
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comb += [
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self.miLa1.trig[:8].eq(self.spi2csr0.csr.dat_w),
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self.miLa1.trig[8:24].eq(self.spi2csr0.csr.adr),
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self.miLa1.trig[24].eq(self.spi2csr0.csr.we),
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self.miLa1.dat[:8].eq(self.spi2csr0.csr.dat_w),
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self.miLa1.dat[8:24].eq(self.spi2csr0.csr.adr),
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self.miLa1.dat[24].eq(self.spi2csr0.csr.we)
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]
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# Spi2Csr
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self.spi2csr0.spi_clk = self.gpio_0[0]
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self.spi2csr0.spi_cs_n = self.gpio_0[1]
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self.spi2csr0.spi_mosi = self.gpio_0[2]
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self.spi2csr0.spi_miso = self.gpio_0[3]
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#
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# Clocking / Reset
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#
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comb += [
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self.cd_sys.clk.eq(self.clk50),
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self.cd_sys.rst.eq(~self.key[0])
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]
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# migIo0
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miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
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# migLa0
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term0 = trigger.Term(trig0_width)
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trigger0 = trigger.Trigger(trig0_width, [term0])
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recorder0 = recorder.Recorder(dat0_width, record_size)
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miLa0 = mila.MiLa(MILA0_ADDR, trigger0, recorder0)
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# migLa1
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term1 = trigger.Term(trig1_width)
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trigger1 = trigger.Trigger(trig1_width, [term1])
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recorder1 = recorder.Recorder(dat1_width, record_size)
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miLa1 = mila.MiLa(MILA1_ADDR, trigger1, recorder1)
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# Spi2Csr
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spi2csr0 = spi2csr.Spi2Csr(16,8)
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# Csr Interconnect
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csrcon0 = csr.Interconnect(spi2csr0.csr,
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[
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miIo0.bank.bus,
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miLa0.trigger.bank.bus,
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miLa0.recorder.bank.bus,
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miLa1.trigger.bank.bus,
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miLa1.recorder.bank.bus,
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])
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comb = []
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sync = []
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#
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# Signal Generator
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#
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# Counter
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cnt_gen = Signal(8)
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sync += [
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cnt_gen.eq(cnt_gen+1)
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]
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# Square
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square_gen = Signal(8)
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sync += [
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If(cnt_gen[7],
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square_gen.eq(255)
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).Else(
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square_gen.eq(0)
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)
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]
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus_re = Signal()
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sinus_gen = Signal(8)
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comb +=[sinus_re.eq(1)]
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sinus_mem = Memory(8, 256, init = sinus)
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sinus_port = sinus_mem.get_port(has_re=True)
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comb += [
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sinus_port.adr.eq(cnt_gen),
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sinus_port.re.eq(sinus_re),
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sinus_gen.eq(sinus_port.dat_r)
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]
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# Signal Selection
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sig_gen = Signal(8)
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comb += [
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If(miIo0.o == 0,
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sig_gen.eq(cnt_gen)
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).Elif(miIo0.o == 1,
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sig_gen.eq(square_gen)
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).Elif(miIo0.o == 2,
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sig_gen.eq(sinus_gen)
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).Else(
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sig_gen.eq(0)
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)
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]
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# Led
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led0 = Signal(8)
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comb += [led0.eq(miIo0.o[:8])]
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#Switch
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sw0 = Signal(8)
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comb += [miIo0.i.eq(sw0)]
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# MigLa0 input
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comb += [
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miLa0.trig.eq(sig_gen),
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miLa0.dat.eq(sig_gen)
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]
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# MigLa1 input
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comb += [
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miLa1.trig[:8].eq(spi2csr0.csr.dat_w),
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miLa1.trig[8:24].eq(spi2csr0.csr.adr),
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miLa1.trig[24].eq(spi2csr0.csr.we),
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miLa1.dat[:8].eq(spi2csr0.csr.dat_w),
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miLa1.dat[8:24].eq(spi2csr0.csr.adr),
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miLa1.dat[24].eq(spi2csr0.csr.we)
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]
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# HouseKeeping
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cd_in = ClockDomain("in")
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in_rst_n = Signal()
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comb += [
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cd_in.rst.eq(~in_rst_n)
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]
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frag = autofragment.from_local()
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frag += Fragment(sync=sync,comb=comb,memories=[sinus_mem])
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cst = Constraints(in_rst_n, cd_in, spi2csr0, led0, sw0)
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src_verilog, vns = verilog.convert(frag,
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cst.get_ios(),
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name="de1",
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clock_domains={
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"sys": cd_in
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},
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return_ns=True)
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src_qsf = cst.get_qsf(vns)
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return (src_verilog, src_qsf)
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frag = autofragment.from_attributes(self)
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frag += Fragment(comb, sync)
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return frag
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@ -0,0 +1,4 @@
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#
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# Clocks
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#
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create_clock -period 50MHz [get_ports clk50]
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