boards/arty: remove specific arty_symbiflow platform and adapt target to use standard platform.
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@ -254,12 +254,12 @@ class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="a7-35"):
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def __init__(self, variant="a7-35", toolchain="vivado"):
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device = {
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"a7-35": "xc7a35ticsg324-1L",
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"a7-100": "xc7a100tcsg324-1"
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}[variant]
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain="vivado")
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XilinxPlatform.__init__(self, device, _io, _connectors, toolchain=toolchain)
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self.toolchain.bitstream_commands = \
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["set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]"]
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self.toolchain.additional_commands = \
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@ -1,35 +0,0 @@
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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from litex.boards.platforms.arty import _io, _connectors
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="a7-35"):
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device = {
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"a7-35": {"part": "xc7a35tcsg324-1", "symbiflow-device": "xc7a50t_test"},
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}[variant]
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XilinxPlatform.__init__(self, device["part"], _io, _connectors, toolchain="symbiflow")
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self.toolchain.symbiflow_device = device["symbiflow-device"]
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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# Prevent GenericPlatform from creating period constraint on input clock
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pass
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def add_period_constraint(self, clk, period, phase=0):
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if clk is None: return
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period, phase)
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@ -9,7 +9,7 @@ import argparse
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from migen import *
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from litex.boards.platforms import arty_symbiflow
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from litex.boards.platforms import arty
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from litex.build.xilinx.symbiflow import symbiflow_build_args, symbiflow_build_argdict
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from litex.soc.cores.clock import *
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@ -22,10 +22,10 @@ from litex.soc.cores.led import LedChaser
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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clk100_ibuf = Signal()
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clk100_buf = Signal()
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clk100_buf = Signal()
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self.specials += Instance("IBUF", i_I=platform.request("clk100"), o_O=clk100_ibuf)
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self.specials += Instance("BUFG", i_I=clk100_ibuf, o_O=clk100_buf)
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@ -34,15 +34,15 @@ class _CRG(Module):
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pll.register_clkin(clk100_buf, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_period_constraint(clk100_buf, 1e9/100e6, 0)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq, 0)
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platform.add_period_constraint(clk100_buf, 1e9/100e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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platform.add_false_path_constraints(clk100_buf, self.cd_sys.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(60e6), with_ethernet=False, with_etherbone=False, **kwargs):
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platform = arty_symbiflow.Platform()
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platform = arty.Platform(toolchain="symbiflow")
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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@ -119,21 +119,21 @@ class TestTargets(unittest.TestCase):
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def test_simple(self):
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platforms = []
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# Xilinx
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platforms += ["minispartan6"] # Spartan6
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platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", "arty_symbiflow"] # Artix7
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platforms += ["kc705", "genesys2"] # Kintex7
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platforms += ["kcu105"] # Kintex Ultrascale
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platforms += ["minispartan6"] # Spartan6
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platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7
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platforms += ["kc705", "genesys2"] # Kintex7
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platforms += ["kcu105"] # Kintex Ultrascale
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# Altera/Intel
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platforms += ["de0nano"] # Cyclone4
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platforms += ["de0nano"] # Cyclone4
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# Lattice
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platforms += ["tinyfpga_bx"] # iCE40
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platforms += ["machxo3"] # MachXO3
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platforms += ["versa_ecp5", "ulx3s"] # ECP5
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platforms += ["tinyfpga_bx"] # iCE40
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platforms += ["machxo3"] # MachXO3
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platforms += ["versa_ecp5", "ulx3s"] # ECP5
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# Microsemi
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platforms += ["avalanche"] # PolarFire
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platforms += ["avalanche"] # PolarFire
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for p in platforms:
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with self.subTest(platform=p):
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