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soc/cores/spi: make sure miso is stable during xfer.

This commit is contained in:
Florent Kermarrec 2020-07-17 11:56:27 +02:00
parent ac35e158c1
commit 8143f1a08b
1 changed files with 3 additions and 2 deletions
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5
litex/soc/cores/spi.py
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@ -113,7 +113,7 @@ class SPIMaster(Module, AutoCSR):
# Master In Slave Out (MISO) capture (captured on spi_clk rising edge) -------------------- # Master In Slave Out (MISO) capture (captured on spi_clk rising edge) --------------------
miso = Signal() miso = Signal()
miso_data = self.miso miso_data = Signal(data_width)
self.sync += [ self.sync += [
If(clk_rise & shift, If(clk_rise & shift,
If(self.loopback, If(self.loopback,
@ -124,7 +124,8 @@ class SPIMaster(Module, AutoCSR):
), ),
If(clk_fall & shift, If(clk_fall & shift,
miso_data.eq(Cat(miso, miso_data)) miso_data.eq(Cat(miso, miso_data))
) ),
If(self.done, self.miso.eq(miso_data)),
] ]
def add_csr(self, with_cs=True, with_loopback=True): def add_csr(self, with_cs=True, with_loopback=True):