litex/build/io: also import CRG (since using DifferentialInput).

This commit is contained in:
Florent Kermarrec 2020-04-10 10:25:21 +02:00
parent 79913e8614
commit 8159b65bee
4 changed files with 27 additions and 6 deletions

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@ -20,9 +20,6 @@ from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII from liteeth.phy.rmii import LiteEthPHYRMII
from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY
# CRG ---------------------------------------------------------------------------------------------- # CRG ----------------------------------------------------------------------------------------------
class _CRG(Module): class _CRG(Module):
@ -78,6 +75,8 @@ class BaseSoC(SoCCore):
# SPI XIP ---------------------------------------------------------------------------------- # SPI XIP ----------------------------------------------------------------------------------
if with_spi_xip: if with_spi_xip:
from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY
spi_xip_size = 1024*1024*8 spi_xip_size = 1024*1024*8
self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x")) self.submodules.spiphy = LiteSPIPHY(platform.request("spiflash4x"))
self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness) self.submodules.spictl = LiteSPI(phy=self.spiphy, endianness=self.cpu.endianness)

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@ -8,7 +8,8 @@ import argparse
import importlib import importlib
from migen import * from migen import *
from migen.genlib.io import CRG
from litex.build.io import CRG
from litex.soc.integration.soc_core import * from litex.soc.integration.soc_core import *
from litex.soc.integration.builder import * from litex.soc.integration.builder import *

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@ -7,10 +7,10 @@ import os
from migen.fhdl.structure import Signal from migen.fhdl.structure import Signal
from migen.genlib.record import Record from migen.genlib.record import Record
from migen.genlib.io import CRG
from litex.gen.fhdl import verilog from litex.gen.fhdl import verilog
from litex.build.io import CRG
from litex.build import tools from litex.build import tools

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@ -1,4 +1,5 @@
# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2015 Sebastien Bourdeauducq <sb@m-labs.hk>
# License: BSD # License: BSD
from migen import * from migen import *
@ -39,7 +40,6 @@ class DifferentialOutput(Special):
def lower(dr): def lower(dr):
raise NotImplementedError("Attempted to use a Differential Output, but platform does not support them") raise NotImplementedError("Attempted to use a Differential Output, but platform does not support them")
# SDR Input/Output --------------------------------------------------------------------------------- # SDR Input/Output ---------------------------------------------------------------------------------
class InferedSDRIO(Module): class InferedSDRIO(Module):
@ -111,3 +111,24 @@ class DDROutput(Special):
@staticmethod @staticmethod
def lower(dr): def lower(dr):
raise NotImplementedError("Attempted to use a DDR output, but platform does not support them") raise NotImplementedError("Attempted to use a DDR output, but platform does not support them")
# Clock Reset Generator ----------------------------------------------------------------------------
class CRG(Module):
def __init__(self, clk, rst=0):
self.clock_domains.cd_sys = ClockDomain()
self.clock_domains.cd_por = ClockDomain(reset_less=True)
if hasattr(clk, "p"):
clk_se = Signal()
self.specials += DifferentialInput(clk.p, clk.n, clk_se)
clk = clk_se
# Power on Reset (vendor agnostic)
int_rst = Signal(reset=1)
self.sync.por += int_rst.eq(rst)
self.comb += [
self.cd_sys.clk.eq(clk),
self.cd_por.clk.eq(clk),
self.cd_sys.rst.eq(int_rst)
]