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target/kc705: allow access to pll_sys signal before BUFG

This commit is contained in:
Yann Sionneau 2015-02-25 18:57:09 +01:00 committed by Sebastien Bourdeauducq
parent 554731ae44
commit 8364fe6674
1 changed files with 3 additions and 3 deletions
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6
targets/kc705.py
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@ -20,7 +20,7 @@ class _CRG(Module):
pll_locked = Signal() pll_locked = Signal()
pll_fb = Signal() pll_fb = Signal()
pll_sys = Signal() self.pll_sys = Signal()
pll_sys4x = Signal() pll_sys4x = Signal()
pll_clk200 = Signal() pll_clk200 = Signal()
self.specials += [ self.specials += [
@ -33,7 +33,7 @@ class _CRG(Module):
i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb, i_CLKIN1=clk200_se, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
# 125MHz # 125MHz
p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys, p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=self.pll_sys,
# 500MHz # 500MHz
p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x, p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
@ -45,7 +45,7 @@ class _CRG(Module):
p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4= p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
), ),
Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk), Instance("BUFG", i_I=self.pll_sys, o_O=self.cd_sys.clk),
Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk), Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk), Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
AsyncResetSynchronizer(self.cd_sys, ~pll_locked), AsyncResetSynchronizer(self.cd_sys, ~pll_locked),