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Merge pull request #2122 from acceleratedtech/accelerated/uart-dynamic-baudrate-for-upstream 

feat: add uart_with_dynamic_baudrate to SoCCore
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enjoy-digital 2024-11-15 09:36:20 +01:00 committed by GitHub
parent 2b3fd723a2 f53178d712
commit 8399c919bd
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3 changed files with 10 additions and 9 deletions
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4
litex/soc/cores/uart.py
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@ -202,14 +202,14 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
else: else:
return stream.SyncFIFO([("data", 8)], depth, buffered=True) return stream.SyncFIFO([("data", 8)], depth, buffered=True)
def UARTPHY(pads, clk_freq, baudrate): def UARTPHY(pads, clk_freq, baudrate, with_dynamic_baudrate=False):
# FT245 Asynchronous FIFO mode (baudrate ignored) # FT245 Asynchronous FIFO mode (baudrate ignored)
if hasattr(pads, "rd_n") and hasattr(pads, "wr_n"): if hasattr(pads, "rd_n") and hasattr(pads, "wr_n"):
from litex.soc.cores.usb_fifo import FT245PHYAsynchronous from litex.soc.cores.usb_fifo import FT245PHYAsynchronous
return FT245PHYAsynchronous(pads, clk_freq) return FT245PHYAsynchronous(pads, clk_freq)
# RS232 # RS232
else: else:
return RS232PHY(pads, clk_freq, baudrate) return RS232PHY(pads, clk_freq, baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
class UART(LiteXModule, UARTInterface): class UART(LiteXModule, UARTInterface):
def __init__(self, phy=None, def __init__(self, phy=None,

10
litex/soc/integration/soc.py
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@ -1511,7 +1511,7 @@ class LiteXSoC(SoC):
self.add_config(name, identifier) self.add_config(name, identifier)
# Add UART ------------------------------------------------------------------------------------- # Add UART -------------------------------------------------------------------------------------
def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16): def add_uart(self, name="uart", uart_name="serial", uart_pads=None, baudrate=115200, fifo_depth=16, with_dynamic_baudrate=False):
# Imports. # Imports.
from litex.soc.cores.uart import UART, UARTCrossover from litex.soc.cores.uart import UART, UARTCrossover
@ -1550,7 +1550,7 @@ class LiteXSoC(SoC):
# Crossover + UARTBone. # Crossover + UARTBone.
elif uart_name in ["crossover+uartbone"]: elif uart_name in ["crossover+uartbone"]:
self.add_uartbone(baudrate=baudrate) self.add_uartbone(baudrate=baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
uart = UARTCrossover(**uart_kwargs) uart = UARTCrossover(**uart_kwargs)
# JTAG UART. # JTAG UART.
@ -1588,7 +1588,7 @@ class LiteXSoC(SoC):
# Regular UART. # Regular UART.
else: else:
from litex.soc.cores.uart import UARTPHY from litex.soc.cores.uart import UARTPHY
uart_phy = UARTPHY(uart_pads, clk_freq=self.sys_clk_freq, baudrate=baudrate) uart_phy = UARTPHY(uart_pads, clk_freq=self.sys_clk_freq, baudrate=baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
uart = UART(uart_phy, **uart_kwargs) uart = UART(uart_phy, **uart_kwargs)
# Add PHY/UART. # Add PHY/UART.
@ -1604,7 +1604,7 @@ class LiteXSoC(SoC):
self.add_constant("UART_POLLING", check_duplicate=False) self.add_constant("UART_POLLING", check_duplicate=False)
# Add UARTbone --------------------------------------------------------------------------------- # Add UARTbone ---------------------------------------------------------------------------------
def add_uartbone(self, name="uartbone", uart_name="serial", clk_freq=None, baudrate=115200, cd="sys"): def add_uartbone(self, name="uartbone", uart_name="serial", clk_freq=None, baudrate=115200, cd="sys", with_dynamic_baudrate=False):
# Imports. # Imports.
from litex.soc.cores import uart from litex.soc.cores import uart
@ -1612,7 +1612,7 @@ class LiteXSoC(SoC):
if clk_freq is None: if clk_freq is None:
clk_freq = self.sys_clk_freq clk_freq = self.sys_clk_freq
self.check_if_exists(name) self.check_if_exists(name)
uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate) uartbone_phy = uart.UARTPHY(self.platform.request(uart_name), clk_freq, baudrate, with_dynamic_baudrate=with_dynamic_baudrate)
uartbone = uart.UARTBone( uartbone = uart.UARTBone(
phy = uartbone_phy, phy = uartbone_phy,
clk_freq = clk_freq, clk_freq = clk_freq,

5
litex/soc/integration/soc_core.py
View File

@ -100,6 +100,7 @@ class SoCCore(LiteXSoC):
uart_name = "serial", uart_name = "serial",
uart_baudrate = 115200, uart_baudrate = 115200,
uart_fifo_depth = 16, uart_fifo_depth = 16,
uart_with_dynamic_baudrate = False,
# Timer parameters. # Timer parameters.
with_timer = True, with_timer = True,
@ -255,11 +256,11 @@ class SoCCore(LiteXSoC):
# Add UARTBone. # Add UARTBone.
if with_uartbone: if with_uartbone:
self.add_uartbone(baudrate=uart_baudrate) self.add_uartbone(baudrate=uart_baudrate, fifo_depth=uart_fifo_depth, with_dynamic_baudrate=with_dynamic_baudrate)
# Add UART. # Add UART.
if with_uart: if with_uart:
self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth) self.add_uart(name="uart", uart_name=uart_name, baudrate=uart_baudrate, fifo_depth=uart_fifo_depth, with_dynamic_baudrate=uart_with_dynamic_baudrate)
# Add JTAGBone. # Add JTAGBone.
if with_jtagbone: if with_jtagbone: