examples: remove direct uses of Fragment

examples/basic/psync.py

@@ -4,10 +4,10 @@ from migen.fhdl import verilog
 from migen.genlib.cdc import *
 
 class XilinxMultiRegImpl(MultiRegImpl):
-	def get_fragment(self):
-		disable_srl = set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
+	def __init__(self, *args, **kwargs):
+		MultiRegImpl.__init__(self, *args, **kwargs)
+		self.specials += set(SynthesisDirective("attribute shreg_extract of {r} is no", r=r)
 			for r in self.regs)
-		return MultiRegImpl.get_fragment(self) + Fragment(specials=disable_srl)
 
 class XilinxMultiReg:
 	@staticmethod

examples/sim/basic1.py

@@ -6,9 +6,13 @@ from migen.sim.generic import Simulator
 
 # Our simple counter, which increments at every cycle
 # and prints its current value in simulation.
-class Counter:
+class Counter(Module):
 	def __init__(self):
 		self.count = Signal(4)
+
+		# At each cycle, increase the value of the count signal.
+		# We do it with convertible/synthesizable FHDL code.
+		self.sync += self.count.eq(self.count + 1)
 	
 	# This function will be called at every cycle.
 	def do_simulation(self, s):
@@ -19,19 +23,11 @@ class Counter:
 		# Count: 2
 		# ...
 		print("Count: " + str(s.rd(self.count)))
-	
-	def get_fragment(self):
-		# At each cycle, increase the value of the count signal.
-		# We do it with convertible/synthesizable FHDL code.
-		sync = [self.count.eq(self.count + 1)]
-		# List our simulation function in the fragment.
-		sim = [self.do_simulation]
-		return Fragment(sync=sync, sim=sim)
 
 def main():
 	dut = Counter()
 	# We do not specify a top-level nor runner object, and use the defaults.
-	sim = Simulator(dut.get_fragment())
+	sim = Simulator(dut)
 	# Since we do not use sim.interrupt, limit the simulation
 	# to some number of cycles.
 	sim.run(20)

examples/sim/basic2.py

@@ -7,11 +7,13 @@ from migen.sim.generic import Simulator, TopLevel
 # A slightly improved counter.
 # Has a clock enable (CE) signal, counts on more bits
 # and resets with a negative number.
-class Counter:
+class Counter(Module):
 	def __init__(self):
 		self.ce = Signal()
 		# Demonstrate negative numbers and signals larger than 32 bits.
 		self.count = Signal((37, True), reset=-5)
+
+		self.sync += If(self.ce, self.count.eq(self.count + 1))
 	
 	def do_simulation(self, s):
 		# Only assert CE every second cycle.
@@ -35,17 +37,12 @@ class Counter:
 	# Cycle: 3 Count: -4
 	# Cycle: 4 Count: -3
 	# ...
-	
-	def get_fragment(self):
-		sync = [If(self.ce, self.count.eq(self.count + 1))]
-		sim = [self.do_simulation]
-		return Fragment(sync=sync, sim=sim)
 
 def main():
 	dut = Counter()
 	# Instantiating the generic top-level ourselves lets us
 	# specify a VCD output file.
-	sim = Simulator(dut.get_fragment(), TopLevel("my.vcd"))
+	sim = Simulator(dut, TopLevel("my.vcd"))
 	sim.run(20)
 
 main()

examples/sim/memory.py

@@ -4,11 +4,11 @@
 from migen.fhdl.std import *
 from migen.sim.generic import Simulator
 
-class Mem:
+class Mem(Module):
 	def __init__(self):
 		# Initialize the beginning of the memory with integers
 		# from 0 to 19.
-		self.mem = Memory(16, 2**12, init=list(range(20)))
+		self.specials.mem = Memory(16, 2**12, init=list(range(20)))
 	
 	def do_simulation(self, s):
 		# Read the memory. Use the cycle counter as address.
@@ -22,13 +22,10 @@ class Mem:
 		# Demonstrate how to interrupt the simulator.
 		if value == 10:
 			s.interrupt = True
-	
-	def get_fragment(self):
-		return Fragment(specials={self.mem}, sim=[self.do_simulation])
 
 def main():
 	dut = Mem()
-	sim = Simulator(dut.get_fragment())
+	sim = Simulator(dut)
 	# No need for a cycle limit here, we use sim.interrupt instead.
 	sim.run()