Fix Trellis build; ULX3S demo boots to BIOS

Signed-off-by: David Shah <dave@ds0.me>

litex/boards/platforms/ulx3s.py

@@ -36,6 +36,8 @@ _io = [
         Subsignal("dm", Pins("U19 E20")),
         IOStandard("LVCMOS33")
     ),
+
+    ("wifi_gpio0", 0, Pins("L2"), IOStandard("LVCMOS33")),
 ]
 
 
@@ -44,4 +46,4 @@ class Platform(LatticePlatform):
     default_clk_period = 10
 
     def __init__(self, **kwargs):
-        LatticePlatform.__init__(self, "LFE5U-85F-6BG381C", _io, **kwargs)
+        LatticePlatform.__init__(self, "LFE5U-45F-6BG381C", _io, **kwargs)

litex/boards/targets/ulx3s.py

@@ -46,6 +46,10 @@ class _CRG(Module):
             sdram_ps_clk = new_sdram_ps_clk
         self.comb += self.cd_sys_ps.clk.eq(sdram_ps_clk)
 
+        # Stop ESP32 from resetting FPGA
+        wifi_gpio0 = platform.request("wifi_gpio0")
+        self.comb += wifi_gpio0.eq(1)
+
 
 class BaseSoC(SoCSDRAM):
     def __init__(self, **kwargs):

litex/build/lattice/prjtrellis.py

@@ -98,10 +98,11 @@ class LatticePrjTrellisToolchain:
             fragment = fragment.get_fragment()
         platform.finalize(fragment)
 
-        top_output = platform.get_verilog(fragment)
+        top_output = platform.get_verilog(fragment, name=build_name)
         named_sc, named_pc = platform.resolve_signals(top_output.ns)
         top_file = build_name + ".v"
         top_output.write(top_file)
+        platform.add_source(top_file)
 
         # generate constraints
         tools.write_to_file(build_name + ".lpf", _build_lpf(named_sc, named_pc))