integration/soc/add_spi_flash: Add LiteSPI initial support (enabled when module is provided).
Test on iCEBreaker in 1X/4X mode for now. In the future, we could probably deprecate support for old SPIFlash core.
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@ -1477,27 +1477,49 @@ class LiteXSoC(SoC):
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self.platform.add_false_path_constraints(self.crg.cd_sys.clk, eth_rx_clk, eth_tx_clk)
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# Add SPI Flash --------------------------------------------------------------------------------
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def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None):
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# Imports.
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from litex.soc.cores.spi_flash import SpiFlash
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def add_spi_flash(self, name="spiflash", mode="4x", dummy_cycles=None, clk_freq=None, module=None, **kwargs):
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# LiteX SPI Flash Core FIXME: Keep it for now but we'll probably deprecate it.
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if module is None:
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# Imports.
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from litex.soc.cores.spi_flash import SpiFlash
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# Checks.
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assert dummy_cycles is not None # FIXME: Get dummy_cycles from SPI Flash
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assert mode in ["1x", "4x"]
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if clk_freq is None: clk_freq = self.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash
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# Checks.
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assert dummy_cycles is not None # FIXME: Get dummy_cycles from SPI Flash
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assert mode in ["1x", "4x"]
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if clk_freq is None: clk_freq = self.clk_freq/2 # FIXME: Get max clk_freq from SPI Flash
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# Core.
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self.check_if_exists(name)
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spiflash = SpiFlash(
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pads = self.platform.request(name if mode == "1x" else name + mode),
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dummy = dummy_cycles,
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div = ceil(self.clk_freq/clk_freq),
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with_bitbang = True,
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endianness = self.cpu.endianness)
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spiflash.add_clk_primitive(self.platform.device)
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setattr(self.submodules, name, spiflash)
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spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x1000000) # FIXME: Get size from SPI Flash
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self.bus.add_slave(name=name, slave=spiflash.bus, region=spiflash_region)
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# Core.
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self.check_if_exists(name)
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spiflash = SpiFlash(
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pads = self.platform.request(name if mode == "1x" else name + mode),
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dummy = dummy_cycles,
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div = ceil(self.clk_freq/clk_freq),
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with_bitbang = True,
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endianness = self.cpu.endianness)
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spiflash.add_clk_primitive(self.platform.device)
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setattr(self.submodules, name, spiflash)
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spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=0x1000000) # FIXME: Get size from SPI Flash
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self.bus.add_slave(name=name, slave=spiflash.bus, region=spiflash_region)
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# LiteSPI.
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else:
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# Imports.
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from litespi.phy.generic import LiteSPIPHY
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from litespi import LiteSPI
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# Checks/Parameters.
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assert mode in ["1x", "4x"]
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if clk_freq is None: clk_freq = self.sys_clk_freq
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# Core.
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self.check_if_exists(name + "_phy")
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self.check_if_exists(name + "_mmap")
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spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
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spiflash_phy = LiteSPIPHY(spiflash_pads, module)
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spiflash_mmap = LiteSPI(spiflash_phy, clk_freq=clk_freq, mmap_endianness=self.cpu.endianness, **kwargs)
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setattr(self.submodules, name + "_phy", spiflash_phy)
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setattr(self.submodules, name + "_mmap", spiflash_mmap)
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spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size, cached=False)
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self.bus.add_slave(name=name, slave=spiflash_mmap.bus, region=spiflash_region)
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# Add SPI SDCard -------------------------------------------------------------------------------
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def add_spi_sdcard(self, name="spisdcard", spi_clk_freq=400e3, software_debug=False):
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