targets/kcu105: move cd_pll4x.
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c97fabb285
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@ -25,13 +25,13 @@ class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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self.clock_domains.cd_clk200 = ClockDomain()
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self.clock_domains.cd_clk200 = ClockDomain()
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# # #
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# # #
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.submodules.pll = pll = USMMCM(speedgrade=-2)
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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self.comb += pll.reset.eq(platform.request("cpu_reset"))
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self.clock_domains.cd_pll4x = ClockDomain(reset_less=True)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.register_clkin(platform.request("clk125"), 125e6)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_pll4x, sys_clk_freq*4, buf=None, with_reset=False)
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pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
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pll.create_clkout(self.cd_clk200, 200e6, with_reset=False)
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