start code adaptation
This commit is contained in:
Florent Kermarrec
parent
0826811047
commit
8477974ef1
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@ -0,0 +1,14 @@
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from migen.fhdl.std import *
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from migen.flow.actor import EndpointDescription
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eth_mtu = 1532
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eth_preamble = 0xD555555555555555
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buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
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def eth_description(dw):
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layout = [
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("d", dw),
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("last_be", dw//8),
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("error", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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@ -1,66 +1,9 @@
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# This file is Copyright (c) 2014 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from liteethernet.common import *
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from liteethernet.mac import LiteEthernetMAC
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from migen.fhdl.std import *
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from migen.bus import wishbone
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from migen.actorlib.fifo import AsyncFIFO
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from migen.actorlib.structuring import Converter, Pipeline
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from migen.bank.eventmanager import SharedIRQ
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from migen.bank.description import *
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from migen.fhdl.simplify import *
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from misoclib.ethmac.common import *
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from misoclib.ethmac.preamble import PreambleInserter, PreambleChecker
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from migen.actorlib.crc import CRC32Inserter, CRC32Checker
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from misoclib.ethmac.last_be import TXLastBE, RXLastBE
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from misoclib.ethmac.sram import SRAMWriter, SRAMReader
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class EthMAC(Module, AutoCSR):
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def __init__(self, phy, interface="wishbone", with_hw_preamble_crc=True, endianness="be"):
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# Preamble / CRC (optional)
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if with_hw_preamble_crc:
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self._hw_preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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preamble_inserter = PreambleInserter(phy.dw)
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preamble_checker = PreambleChecker(phy.dw)
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self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
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self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
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# CRC insert/check
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crc32_inserter = CRC32Inserter(eth_description(phy.dw))
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crc32_checker = CRC32Checker(eth_description(phy.dw))
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self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
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self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
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# Delimiters
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tx_last_be = TXLastBE(phy.dw)
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rx_last_be = RXLastBE(phy.dw)
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self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
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self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
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# Converters
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reverse = endianness == "be"
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tx_converter = Converter(eth_description(32), eth_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_description(phy.dw), eth_description(32), reverse=reverse)
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self.submodules += RenameClockDomains(tx_converter, "eth_tx")
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self.submodules += RenameClockDomains(rx_converter, "eth_rx")
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_description(32), 4)
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rx_cdc = AsyncFIFO(eth_description(32), 4)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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# Graph
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if with_hw_preamble_crc:
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rx_pipeline = [phy, preamble_checker, crc32_checker, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, crc32_inserter, preamble_inserter, phy]
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else:
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rx_pipeline = [phy, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, phy]
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self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
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self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
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class LiteEthernetMAC(Module, AutoCSR):
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def __init__(self, phy, frontend="wishbone", with_hw_preamble_crc=True, endianness="be"):
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self.submodules.core = LiteEthernetMAC(phy, with_hw_preamble, endianness)
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if interface == "wishbone":
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nrxslots = 2
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@ -0,0 +1,54 @@
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from liteethernet.common import *
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from liteethernet.mac.common import *
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from liteethernet.mac.preamble import PreambleInserter, PreambleChecker
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from liteethernet.mac.crc import CRC32Inserter, CRC32Checker
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from liteethernet.mac.last_be import TXLastBE, RXLastBE
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class LiteEthernetMACCore(Module, AutoCSR):
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def __init__(self, phy, with_hw_preamble_crc=True, endianness="be"):
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# Preamble / CRC (optional)
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if with_hw_preamble_crc:
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self._hw_preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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preamble_inserter = PreambleInserter(phy.dw)
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preamble_checker = PreambleChecker(phy.dw)
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self.submodules += RenameClockDomains(preamble_inserter, "eth_tx")
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self.submodules += RenameClockDomains(preamble_checker, "eth_rx")
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# CRC insert/check
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crc32_inserter = CRC32Inserter(eth_description(phy.dw))
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crc32_checker = CRC32Checker(eth_description(phy.dw))
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self.submodules += RenameClockDomains(crc32_inserter, "eth_tx")
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self.submodules += RenameClockDomains(crc32_checker, "eth_rx")
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# Delimiters
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tx_last_be = TXLastBE(phy.dw)
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rx_last_be = RXLastBE(phy.dw)
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self.submodules += RenameClockDomains(tx_last_be, "eth_tx")
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self.submodules += RenameClockDomains(rx_last_be, "eth_rx")
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# Converters
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reverse = endianness == "be"
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tx_converter = Converter(eth_description(32), eth_description(phy.dw), reverse=reverse)
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rx_converter = Converter(eth_description(phy.dw), eth_description(32), reverse=reverse)
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self.submodules += RenameClockDomains(tx_converter, "eth_tx")
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self.submodules += RenameClockDomains(rx_converter, "eth_rx")
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# Cross Domain Crossing
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tx_cdc = AsyncFIFO(eth_description(32), 4)
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rx_cdc = AsyncFIFO(eth_description(32), 4)
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self.submodules += RenameClockDomains(tx_cdc, {"write": "sys", "read": "eth_tx"})
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self.submodules += RenameClockDomains(rx_cdc, {"write": "eth_rx", "read": "sys"})
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# Graph
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if with_hw_preamble_crc:
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rx_pipeline = [phy, preamble_checker, crc32_checker, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, crc32_inserter, preamble_inserter, phy]
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else:
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rx_pipeline = [phy, rx_last_be, rx_converter, rx_cdc]
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tx_pipeline = [tx_cdc, tx_converter, tx_last_be, phy]
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self.submodules.rx_pipeline = Pipeline(*rx_pipeline)
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self.submodules.tx_pipeline = Pipeline(*tx_pipeline)
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self.sink, self.source = self.tx_pipeline.sink, self.rx_pipeline.source
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@ -0,0 +1,284 @@
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from migen.fhdl.std import *
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from migen.genlib.fsm import FSM, NextState
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from migen.genlib.record import *
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from migen.genlib.misc import optree, chooser
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from migen.genlib.crc import *
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from migen.flow.actor import Sink, Source
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from migen.actorlib.fifo import SyncFIFO
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from collections import OrderedDict
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class CRCEngine(Module):
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"""Cyclic Redundancy Check Engine
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Compute next CRC value from last CRC value and data input using
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an optimized asynchronous LFSR.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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width : int
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Width of the CRC.
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polynom : int
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Polynom of the CRC (ex: 0x04C11DB7 for IEEE 802.3 CRC)
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Attributes
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----------
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d : in
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Data input.
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last : in
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last CRC value.
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next :
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next CRC value.
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"""
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def __init__(self, dat_width, width, polynom):
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self.d = Signal(dat_width)
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self.last = Signal(width)
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self.next = Signal(width)
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###
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def _optimize_eq(l):
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"""
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Replace even numbers of XORs in the equation
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with an equivalent XOR
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"""
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d = OrderedDict()
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for e in l:
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if e in d:
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d[e] += 1
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else:
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d[e] = 1
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r = []
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for key, value in d.items():
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if value%2 != 0:
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r.append(key)
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return r
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# compute and optimize CRC's LFSR
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curval = [[("state", i)] for i in range(width)]
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for i in range(dat_width):
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feedback = curval.pop() + [("din", i)]
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for j in range(width-1):
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if (polynom & (1<<(j+1))):
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curval[j] += feedback
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curval[j] = _optimize_eq(curval[j])
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curval.insert(0, feedback)
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# implement logic
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for i in range(width):
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xors = []
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for t, n in curval[i]:
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if t == "state":
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xors += [self.last[n]]
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elif t == "din":
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xors += [self.d[n]]
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self.comb += self.next[i].eq(optree("^", xors))
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@DecorateModule(InsertReset)
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@DecorateModule(InsertCE)
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class CRC32(Module):
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"""IEEE 802.3 CRC
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Implement an IEEE 802.3 CRC generator/checker.
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Parameters
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----------
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dat_width : int
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Width of the data bus.
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Attributes
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----------
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d : in
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Data input.
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value : out
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CRC value (used for generator).
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error : out
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CRC error (used for checker).
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"""
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width = 32
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polynom = 0x04C11DB7
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init = 2**width-1
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check = 0xC704DD7B
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def __init__(self, dat_width):
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self.d = Signal(dat_width)
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self.value = Signal(self.width)
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self.error = Signal()
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###
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self.submodules.engine = CRCEngine(dat_width, self.width, self.polynom)
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reg = Signal(self.width, reset=self.init)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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self.engine.d.eq(self.d),
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self.engine.last.eq(reg),
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self.value.eq(~reg[::-1]),
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self.error.eq(self.engine.next != self.check)
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]
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class CRCInserter(Module):
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"""CRC Inserter
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Append a CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input without CRC.
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source : out
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Packets output with CRC.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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crc = crc_class(dw)
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fsm = FSM(reset_state="IDLE")
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self.submodules += crc, fsm
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fsm.act("IDLE",
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crc.reset.eq(1),
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sink.ack.eq(1),
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If(sink.stb & sink.sop,
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sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(sink.stb & source.ack),
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crc.d.eq(sink.d),
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Record.connect(sink, source),
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source.eop.eq(0),
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If(sink.stb & sink.eop & source.ack,
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NextState("INSERT"),
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)
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)
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ratio = crc.width//dw
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if ratio > 1:
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cnt = Signal(max=ratio, reset=ratio-1)
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cnt_done = Signal()
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fsm.act("INSERT",
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source.stb.eq(1),
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chooser(crc.value, cnt, source.d, reverse=True),
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If(cnt_done,
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source.eop.eq(1),
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If(source.ack, NextState("IDLE"))
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)
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)
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self.comb += cnt_done.eq(cnt == 0)
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self.sync += \
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If(fsm.ongoing("IDLE"),
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cnt.eq(cnt.reset)
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).Elif(fsm.ongoing("INSERT") & ~cnt_done,
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cnt.eq(cnt - source.ack)
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)
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else:
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fsm.act("INSERT",
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source.stb.eq(1),
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source.eop.eq(1),
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source.d.eq(crc.value),
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If(source.ack, NextState("IDLE"))
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Inserter(CRCInserter):
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def __init__(self, layout):
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CRCInserter.__init__(self, CRC32, layout)
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class CRCChecker(Module):
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"""CRC Checker
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Check CRC at the end of each packet.
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Parameters
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----------
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layout : layout
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Layout of the dataflow.
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Attributes
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----------
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sink : in
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Packets input with CRC.
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source : out
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Packets output without CRC and "error" set to 0
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on eop when CRC OK / set to 1 when CRC KO.
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"""
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def __init__(self, crc_class, layout):
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self.sink = sink = Sink(layout)
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self.source = source = Source(layout)
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self.busy = Signal()
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###
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dw = flen(sink.d)
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crc = crc_class(dw)
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self.submodules += crc
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ratio = crc.width//dw
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error = Signal()
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fifo = InsertReset(SyncFIFO(layout, ratio + 1))
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self.submodules += fifo
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fsm = FSM(reset_state="RESET")
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self.submodules += fsm
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fifo_in = Signal()
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fifo_out = Signal()
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fifo_full = Signal()
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self.comb += [
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fifo_full.eq(fifo.fifo.level == ratio),
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fifo_in.eq(sink.stb & (~fifo_full | fifo_out)),
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fifo_out.eq(source.stb & source.ack),
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Record.connect(sink, fifo.sink),
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fifo.sink.stb.eq(fifo_in),
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self.sink.ack.eq(fifo_in),
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source.stb.eq(sink.stb & fifo_full),
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source.sop.eq(fifo.source.sop),
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source.eop.eq(sink.eop),
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fifo.source.ack.eq(fifo_out),
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source.payload.eq(fifo.source.payload),
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source.error.eq(sink.error | crc.error),
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]
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fsm.act("RESET",
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crc.reset.eq(1),
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fifo.reset.eq(1),
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NextState("IDLE"),
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)
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fsm.act("IDLE",
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crc.d.eq(sink.d),
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If(sink.stb & sink.sop & sink.ack,
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crc.ce.eq(1),
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NextState("COPY")
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)
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)
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fsm.act("COPY",
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crc.d.eq(sink.d),
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If(sink.stb & sink.ack,
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crc.ce.eq(1),
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If(sink.eop,
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NextState("RESET")
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)
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)
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)
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self.comb += self.busy.eq(~fsm.ongoing("IDLE"))
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class CRC32Checker(CRCChecker):
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def __init__(self, layout):
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CRCChecker.__init__(self, CRC32, layout)
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@ -2,7 +2,8 @@ from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.flow.actor import Sink, Source
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from misoclib.ethmac.common import *
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from liteethernet.common import *
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from liteethernet.mac.common import *
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class TXLastBE(Module):
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def __init__(self, d_w):
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|
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@ -4,7 +4,8 @@ from migen.genlib.misc import chooser
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from migen.genlib.record import *
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from migen.flow.actor import Sink, Source
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from misoclib.ethmac.common import *
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from liteethernet.common import *
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from liteethernet.ethmac.common import *
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class PreambleInserter(Module):
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def __init__(self, d_w):
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|
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@ -6,7 +6,8 @@ from migen.flow.actor import Sink, Source
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from migen.bank.description import *
|
||||
from migen.bank.eventmanager import *
|
||||
|
||||
from misoclib.ethmac.common import *
|
||||
from liteethernet.common import *
|
||||
from liteethernet.mac.common import *
|
||||
|
||||
class SRAMWriter(Module, AutoCSR):
|
||||
def __init__(self, depth, nslots=2):
|
||||
|
|
|
|||
|
|
@ -0,0 +1,39 @@
|
|||
from liteethernet.common import *
|
||||
from liteethernet.mac import LiteEthernetMAC
|
||||
|
||||
class LiteEthernetMACWishboneInterface(Module, AutoCSR):
|
||||
def __init__(self, nrxslots=2, ntxslots=2):
|
||||
self.sink = Sink(mac_description(dw))
|
||||
self.source = Source(max_description(dw))
|
||||
self.bus = wishbone.Interface()
|
||||
|
||||
###
|
||||
|
||||
# SRAM Storage
|
||||
sram_depth = buffer_depth//(32//8)
|
||||
self.submodules.sram_writer = SRAMWriter(sram_depth, nrxslots)
|
||||
self.submodules.sram_reader = SRAMReader(sram_depth, ntxslots)
|
||||
self.submodules.ev = SharedIRQ(self.sram_writer.ev, self.sram_reader.ev)
|
||||
self.comb += [
|
||||
Record.connect(self.sink, self.sram_writer.sink),
|
||||
Record.connect(self.sram_reader.source, self.source)
|
||||
]
|
||||
|
||||
# Interface
|
||||
wb_rx_sram_ifs = [wishbone.SRAM(self.sram_writer.mems[n], read_only=True)
|
||||
for n in range(nrxslots)]
|
||||
# TODO: FullMemoryWE should move to Mibuild
|
||||
wb_tx_sram_ifs = [FullMemoryWE(wishbone.SRAM(self.sram_reader.mems[n], read_only=False))
|
||||
for n in range(ntxslots)]
|
||||
wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
|
||||
|
||||
wb_slaves = []
|
||||
decoderoffset = log2_int(sram_depth)
|
||||
decoderbits = log2_int(len(wb_sram_ifs))
|
||||
for n, wb_sram_if in enumerate(wb_sram_ifs):
|
||||
def slave_filter(a, v=n):
|
||||
return a[decoderoffset:decoderoffset+decoderbits] == v
|
||||
wb_slaves.append((slave_filter, wb_sram_if.bus))
|
||||
self.submodules += wb_sram_if
|
||||
wb_con = wishbone.Decoder(self.bus, wb_slaves, register=True)
|
||||
self.submodules += wb_con
|
||||
|
|
@ -3,14 +3,12 @@ from migen.flow.actor import Sink, Source
|
|||
from migen.bank.description import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from misoclib.ethmac.common import *
|
||||
from liteethernet.common import *
|
||||
|
||||
class GMIIPHYTX(Module):
|
||||
def __init__(self, pads):
|
||||
self.sink = sink = Sink(eth_description(8))
|
||||
|
||||
###
|
||||
|
||||
self.sync += [
|
||||
pads.tx_er.eq(0),
|
||||
pads.tx_en.eq(sink.stb),
|
||||
|
|
@ -21,9 +19,7 @@ class GMIIPHYTX(Module):
|
|||
class GMIIPHYRX(Module):
|
||||
def __init__(self, pads):
|
||||
self.source = source = Source(eth_description(8))
|
||||
|
||||
###
|
||||
|
||||
dv_d = Signal()
|
||||
self.sync += dv_d.eq(pads.dv)
|
||||
|
||||
|
|
@ -45,9 +41,7 @@ class GMIIPHYRX(Module):
|
|||
class GMIIPHYCRG(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
###
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.specials += [
|
||||
|
|
@ -3,14 +3,12 @@ from migen.flow.actor import Sink, Source
|
|||
from migen.bank.description import *
|
||||
from migen.genlib.record import *
|
||||
|
||||
from misoclib.ethmac.common import *
|
||||
from liteethernet.common import *
|
||||
|
||||
class LoopbackPHYCRG(Module, AutoCSR):
|
||||
def __init__(self):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
###
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
self.clock_domains.cd_eth_tx = ClockDomain()
|
||||
self.comb += [
|
||||
|
|
@ -4,14 +4,12 @@ from migen.flow.actor import Sink, Source
|
|||
from migen.bank.description import *
|
||||
from migen.genlib.resetsync import AsyncResetSynchronizer
|
||||
|
||||
from misoclib.ethmac.common import *
|
||||
from liteethernet.common import *
|
||||
|
||||
class MIIPHYTX(Module):
|
||||
def __init__(self, pads):
|
||||
self.sink = sink = Sink(eth_description(8))
|
||||
|
||||
###
|
||||
|
||||
tx_en_r = Signal()
|
||||
tx_data_r = Signal(4)
|
||||
self.sync += [
|
||||
|
|
@ -48,9 +46,7 @@ class MIIPHYTX(Module):
|
|||
class MIIPHYRX(Module):
|
||||
def __init__(self, pads):
|
||||
self.source = source = Source(eth_description(8))
|
||||
|
||||
###
|
||||
|
||||
sop = source.sop
|
||||
set_sop = Signal()
|
||||
clr_sop = Signal()
|
||||
|
|
@ -102,9 +98,7 @@ class MIIPHYRX(Module):
|
|||
class MIIPHYCRG(Module, AutoCSR):
|
||||
def __init__(self, clock_pads, pads):
|
||||
self._reset = CSRStorage()
|
||||
|
||||
###
|
||||
|
||||
self.sync.base50 += clock_pads.phy.eq(~clock_pads.phy)
|
||||
|
||||
self.clock_domains.cd_eth_rx = ClockDomain()
|
||||
Loading…
Reference in New Issue