Merge pull request #1631 from trabucayre/fix_get_extension
add a proxy method to access bitstream extension
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commit
847fac0a81
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@ -13,7 +13,10 @@ from litex.build.altera import common, quartus
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# AlteraPlatform -----------------------------------------------------------------------------------
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class AlteraPlatform(GenericPlatform):
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bitstream_ext = ".sof"
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_bitstream_ext = {
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"sram" : ".sof",
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"flash" : ".rbf"
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}
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create_rbf = True
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_supported_toolchains = ["quartus"]
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@ -13,7 +13,7 @@ from litex.build.anlogic import common, anlogic
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# AnlogicPlatform ----------------------------------------------------------------------------------
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class AnlogicPlatform(GenericPlatform):
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bitstream_ext = ".fs"
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_bitstream_ext = ".bit"
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_supported_toolchains = ["td"]
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@ -16,7 +16,10 @@ from litex.build.efinix import EfinixDbParser
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# EfinixPlatform -----------------------------------------------------------------------------------
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class EfinixPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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_bitstream_ext = {
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"sram" : ".bit",
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"flash" : ".hex"
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}
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_supported_toolchains = ["efinity"]
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@ -323,6 +323,9 @@ class ConstraintManager:
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class GenericPlatform:
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device_family = None
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_bitstream_ext = None # None by default, overridden by vendor platform, may
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# be a string when same extension is used for sram and
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# flash. A dict must be provided otherwise
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def __init__(self, device, io, connectors=[], name=None):
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self.toolchain = None
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@ -463,6 +466,31 @@ class GenericPlatform:
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def build(self, fragment):
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raise NotImplementedError("GenericPlatform.build must be overloaded")
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def get_bitstream_extension(self, mode="sram"):
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"""
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Return the bitstream's extension according to mode (sram / flash).
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The default (generic) implementation check if `self._bitstream_ext`
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is a dict or a string. For former case it return extension using `mode`
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parameter, in latter case simply return `self._bitstream_ext`'s value.
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When this behaviour is not adapted this method must be overriden by
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a specific one at vendor level.
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Parameters
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----------
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mode: str
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bitstream destination (must be sram or flash)
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Returns
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-------
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bitstream extension: str
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"""
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if self._bitstream_ext is None:
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return None
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elif type(self._bitstream_ext) == dict:
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return self._bitstream_ext[mode]
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else:
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return self._bitstream_ext
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def create_programmer(self):
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raise NotImplementedError
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@ -13,7 +13,7 @@ from litex.build.gowin import common, gowin
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# GowinPlatform ------------------------------------------------------------------------------------
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class GowinPlatform(GenericPlatform):
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bitstream_ext = ".fs"
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_bitstream_ext = ".fs"
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_supported_toolchains = ["gowin", "apicula"]
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@ -11,7 +11,7 @@ from litex.build.lattice import common, diamond, icestorm, trellis, radiant, oxi
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# LatticePlatform ----------------------------------------------------------------------------------
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class LatticePlatform(GenericPlatform):
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bitstream_ext = ".bit"
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_bitstream_ext = ".bit"
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_supported_toolchains = {
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"ice40" : ["icestorm"],
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@ -26,7 +26,7 @@ class LatticePlatform(GenericPlatform):
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elif toolchain == "trellis":
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self.toolchain = trellis.LatticeTrellisToolchain()
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elif toolchain == "icestorm":
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self.bitstream_ext = ".bin"
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self._bitstream_ext = ".bin"
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self.toolchain = icestorm.LatticeIceStormToolchain()
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elif toolchain == "radiant":
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self.toolchain = radiant.LatticeRadiantToolchain()
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@ -10,7 +10,7 @@ from litex.build.microsemi import common, libero_soc
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# MicrosemiPlatform --------------------------------------------------------------------------------
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class MicrosemiPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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_bitstream_ext = ".bit"
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_supported_toolchains = ["libero_soc_polarfire"]
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@ -12,7 +12,7 @@ from litex.build.osfpga import common, osfpga
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# OSFPGAPlatform -----------------------------------------------------------------------------------
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class OSFPGAPlatform(GenericPlatform):
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bitstream_ext = ".bin"
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_bitstream_ext = ".bin"
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_supported_toolchains = ["osfpga"]
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@ -12,7 +12,7 @@ from litex.build.quicklogic import common, f4pga
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# QuickLogicPlatform -------------------------------------------------------------------------------
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class QuickLogicPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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_bitstream_ext = ".bit"
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_supported_toolchains = ["f4pga"]
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@ -14,7 +14,10 @@ from litex.build.xilinx import common, vivado, ise, yosys_nextpnr
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# XilinxPlatform -----------------------------------------------------------------------------------
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class XilinxPlatform(GenericPlatform):
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bitstream_ext = ".bit"
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_bitstream_ext = {
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"sram" : ".bit",
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"flash" : ".bin"
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}
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_supported_toolchains = {
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"spartan6" : ["ise"],
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@ -382,10 +382,7 @@ class Builder:
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def get_bitstream_filename(self, mode="sram", ext=None):
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assert mode in ["sram", "flash"]
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if ext is None:
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ext = {
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"sram" : self.soc.platform.bitstream_ext,
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"flash" : ".bin" # FIXME.
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}[mode]
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ext = self.soc.platform.get_bitstream_extension(mode)
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return os.path.join(self.gateware_dir, self.soc.get_build_name() + ext)
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# Builder Arguments --------------------------------------------------------------------------------
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