use PacketBuffer for udp loopback
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6bf40c4010
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8497f6b906
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@ -247,3 +247,81 @@ class BufferizeEndpoints(ModuleDecorator):
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self.comb += Record.connect(source, buf.d)
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self.comb += Record.connect(source, buf.d)
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setattr(self, name, buf.q)
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setattr(self, name, buf.q)
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class EndpointPacketStatus(Module):
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def __init__(self, endpoint):
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self.start = Signal()
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self.done = Signal()
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self.ongoing = Signal()
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ongoing = Signal()
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self.comb += [
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self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
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self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
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]
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self.sync += \
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If(self.start,
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ongoing.eq(1)
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).Elif(self.done,
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ongoing.eq(0)
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)
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self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
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class PacketBuffer(Module):
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def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
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self.sink = sink = Sink(description)
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self.source = source = Source(description)
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###
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sink_status = EndpointPacketStatus(self.sink)
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source_status = EndpointPacketStatus(self.source)
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self.submodules += sink_status, source_status
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# store incoming packets
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# cmds
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def cmd_description():
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layout = [("error", 1)]
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return EndpointDescription(layout)
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cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
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self.submodules += cmd_fifo
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self.comb += [
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cmd_fifo.sink.stb.eq(sink_status.done),
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cmd_fifo.sink.error.eq(sink.error)
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]
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# data
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data_fifo = SyncFIFO(description, data_depth, buffered=True)
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self.submodules += data_fifo
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self.comb += [
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Record.connect(self.sink, data_fifo.sink),
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data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
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self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
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]
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# output packets
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self.fsm = fsm = FSM(reset_state="IDLE")
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self.submodules += fsm
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fsm.act("IDLE",
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If(cmd_fifo.source.stb,
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NextState("SEEK_SOP")
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)
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)
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fsm.act("SEEK_SOP",
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If(~data_fifo.source.sop,
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data_fifo.source.ack.eq(1)
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).Else(
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NextState("OUTPUT")
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)
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)
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fsm.act("OUTPUT",
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Record.connect(data_fifo.source, self.source),
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self.source.error.eq(cmd_fifo.source.error),
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If(source_status.done,
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cmd_fifo.source.ack.eq(1),
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NextState("IDLE")
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)
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)
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# compute almost full
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if almost_full is not None:
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self.almost_full = Signal()
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self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
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@ -69,7 +69,7 @@ class LiteEthIPTX(Module):
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self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
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self.submodules.checksum = checksum = LiteEthIPV4Checksum(skip_checksum=True)
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self.comb += [
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self.comb += [
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checksum.ce.eq(sink.stb & sink.sop),
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checksum.ce.eq(sink.stb & sink.sop),
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checksum.reset.eq(source.stb & source.eop)
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checksum.reset.eq(source.stb & source.eop & source.ack)
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]
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]
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self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer()
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self.submodules.packetizer = packetizer = LiteEthIPV4Packetizer()
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@ -116,11 +116,10 @@ class UDPSoC(GenSoC, AutoCSR):
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# Create loopback on UDP port 6000
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# Create loopback on UDP port 6000
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loopback_port = self.core.udp.crossbar.get_port(6000)
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loopback_port = self.core.udp.crossbar.get_port(6000)
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loopback_fifo = SyncFIFO(eth_udp_user_description(8), 8192, buffered=True)
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self.submodules.loopback_buffer = PacketBuffer(eth_udp_user_description(8), 8192, 8)
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self.submodules += loopback_fifo
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self.comb += [
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self.comb += [
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Record.connect(loopback_port.source, loopback_fifo.sink),
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Record.connect(loopback_port.source, self.loopback_buffer.sink),
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Record.connect(loopback_fifo.source, loopback_port.sink)
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Record.connect(self.loopback_buffer.source, loopback_port.sink)
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]
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]
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class UDPSoCDevel(UDPSoC, AutoCSR):
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class UDPSoCDevel(UDPSoC, AutoCSR):
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@ -174,6 +173,18 @@ class UDPSoCDevel(UDPSoC, AutoCSR):
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self.core.ip.crossbar.master.sink.ip_address,
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self.core.ip.crossbar.master.sink.ip_address,
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self.core.ip.crossbar.master.sink.protocol,
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self.core.ip.crossbar.master.sink.protocol,
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self.loopback_buffer.sink.stb,
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self.loopback_buffer.sink.sop,
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self.loopback_buffer.sink.eop,
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self.loopback_buffer.sink.ack,
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self.loopback_buffer.sink.data,
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self.loopback_buffer.source.stb,
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self.loopback_buffer.source.sop,
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self.loopback_buffer.source.eop,
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self.loopback_buffer.source.ack,
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self.loopback_buffer.source.data,
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self.phy.sink.stb,
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self.phy.sink.stb,
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self.phy.sink.sop,
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self.phy.sink.sop,
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self.phy.sink.eop,
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self.phy.sink.eop,
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@ -197,7 +208,7 @@ class UDPSoCDevel(UDPSoC, AutoCSR):
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self.core_arp_table_fsm_state,
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self.core_arp_table_fsm_state,
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)
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)
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self.submodules.la = LiteScopeLA(debug, 2048)
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self.submodules.la = LiteScopeLA(debug, 4096)
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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self.la.trigger.add_port(LiteScopeTerm(self.la.dw))
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atexit.register(self.exit, platform)
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atexit.register(self.exit, platform)
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@ -12,10 +12,13 @@ conditions = {}
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conditions = {
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conditions = {
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"udpsocdevel_mac_rx_cdc_source_stb" : 1
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"udpsocdevel_mac_rx_cdc_source_stb" : 1
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}
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}
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conditions = {
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"core_udp_tx_fsm_state" : 1
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}
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la.configure_term(port=0, cond=conditions)
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la.configure_term(port=0, cond=conditions)
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la.configure_sum("term")
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la.configure_sum("term")
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# Run Logic Analyzer
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# Run Logic Analyzer
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la.run(offset=64, length=1024)
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la.run(offset=2048, length=4000)
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while not la.done():
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while not la.done():
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pass
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pass
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@ -51,7 +51,7 @@ rx_sock.bind(("", udp_port))
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def receive():
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def receive():
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rx_seed = 0
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rx_seed = 0
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while rx_seed < test_size:
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while rx_seed < test_size:
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data, addr = rx_sock.recvfrom(1024)
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data, addr = rx_sock.recvfrom(8192)
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rx_packet = []
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rx_packet = []
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for byte in data:
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for byte in data:
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rx_packet.append(int(byte))
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rx_packet.append(int(byte))
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@ -64,7 +64,7 @@ def send():
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while tx_seed < test_size:
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while tx_seed < test_size:
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tx_packet, tx_seed = generate_packet(tx_seed, 1024)
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tx_packet, tx_seed = generate_packet(tx_seed, 1024)
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tx_sock.sendto(bytes(tx_packet), (fpga_ip, udp_port))
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tx_sock.sendto(bytes(tx_packet), (fpga_ip, udp_port))
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time.sleep(0.001) # XXX: FIXME
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time.sleep(0.001) # XXX: FIXME, Python limitation?
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receive_thread = threading.Thread(target=receive)
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receive_thread = threading.Thread(target=receive)
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receive_thread.start()
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receive_thread.start()
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@ -73,7 +73,7 @@ send_thread = threading.Thread(target=send)
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send_thread.start()
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send_thread.start()
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try:
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try:
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send_thread.join()
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send_thread.join(10)
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receive_thread.join()
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receive_thread.join(0.1)
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except KeyboardInterrupt:
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except KeyboardInterrupt:
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pass
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pass
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