liteeth/mac/core: add with_padding option (enabled by default) and change with_hw_preamble_crc option to with_preamble_crc
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@ -4,7 +4,9 @@ from misoclib.com.liteeth.mac.core import gap, preamble, crc, padding, last_be
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from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
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from misoclib.com.liteeth.phy.sim import LiteEthPHYSim
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class LiteEthMACCore(Module, AutoCSR):
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class LiteEthMACCore(Module, AutoCSR):
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def __init__(self, phy, dw, endianness="big", with_hw_preamble_crc=True):
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def __init__(self, phy, dw, endianness="big",
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with_preamble_crc=True,
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with_padding=True):
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if dw < phy.dw:
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if dw < phy.dw:
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
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raise ValueError("Core data width({}) must be larger than PHY data width({})".format(dw, phy.dw))
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@ -24,9 +26,9 @@ class LiteEthMACCore(Module, AutoCSR):
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if isinstance(phy, LiteEthPHYSim):
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if isinstance(phy, LiteEthPHYSim):
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# In simulation, avoid CRC/Preamble to enable direct connection
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# In simulation, avoid CRC/Preamble to enable direct connection
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# to the Ethernet tap.
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# to the Ethernet tap.
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self._hw_preamble_crc = CSRStatus(reset=1)
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self._preamble_crc = CSRStatus(reset=1)
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elif with_hw_preamble_crc:
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elif with_preamble_crc:
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self._hw_preamble_crc = CSRStatus(reset=1)
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self._preamble_crc = CSRStatus(reset=1)
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# Preamble insert/check
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# Preamble insert/check
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preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
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preamble_inserter = preamble.LiteEthMACPreambleInserter(phy.dw)
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preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
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preamble_checker = preamble.LiteEthMACPreambleChecker(phy.dw)
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@ -43,6 +45,7 @@ class LiteEthMACCore(Module, AutoCSR):
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rx_pipeline += [preamble_checker, crc32_checker]
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rx_pipeline += [preamble_checker, crc32_checker]
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# Padding
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# Padding
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if with_padding:
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padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
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padding_inserter = padding.LiteEthMACPaddingInserter(phy.dw, 60)
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padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
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padding_checker = padding.LiteEthMACPaddingChecker(phy.dw, 60)
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self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
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self.submodules += RenameClockDomains(padding_inserter, "eth_tx")
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@ -12,7 +12,7 @@
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#define ETHERTYPE_ARP 0x0806
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#define ETHERTYPE_ARP 0x0806
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#define ETHERTYPE_IP 0x0800
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#define ETHERTYPE_IP 0x0800
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#ifdef CSR_ETHMAC_HW_PREAMBLE_CRC_ADDR
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#ifdef CSR_ETHMAC_PREAMBLE_CRC_ADDR
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#define HW_PREAMBLE_CRC
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#define HW_PREAMBLE_CRC
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#endif
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#endif
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