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bank: remove RE signal for field registers

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This commit is contained in:
Sebastien Bourdeauducq 2012-10-09 19:07:53 +02:00
parent e410973352
commit 85081793cf
2 changed files with 2 additions and 8 deletions
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2
migen/bank/csrgen.py
View file

@ -29,7 +29,6 @@ class Bank:
self.interface.we & \
(self.interface.adr[:nbits] == Constant(i, BV(nbits)))))
elif isinstance(reg, RegisterFields):
sync.append(reg.re.eq(0))
bwra = [Constant(i, BV(nbits))]
offset = 0
for field in reg.fields:
@ -37,7 +36,6 @@ class Bank:
bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
offset += field.size
if len(bwra) > 1:
bwra.append(reg.re.eq(1))
bwcases.append(bwra)
# commit atomic writes
for field in reg.fields:

8
migen/bank/description.py
View file

@ -28,13 +28,9 @@ class Field:
self.we = Signal()
class RegisterFields:
def __init__(self, name, fields, re=None):
def __init__(self, name, fields):
self.name = name
self.fields = fields
if re is None:
self.re = Signal()
else:
self.re = re
class RegisterField(RegisterFields):
def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False):
@ -111,7 +107,7 @@ def expand_description(description, busword):
else:
f.append(field)
if f:
d.append(RegisterFields(reg.name, f, reg.re))
d.append(RegisterFields(reg.name, f))
else:
raise TypeError
return d