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cpu/vexriscv: update submodule

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This commit is contained in:
Florent Kermarrec 2019-06-07 18:36:46 +02:00
parent 755a2660ba
commit 850b311d04
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/cpu/vexriscv/verilog

@ -1 +1 @@
Subproject commit c6dfccaaa3c830b8c9c5037bbd4e1a8d43ca5bf0
Subproject commit 4b5a515d4bbb22df0eb44a6e53cc76b3da1ff470