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soc/cores/cpu/naxriscv/core: adding argument to enable rvc extension

This commit is contained in:
Gwenhael Goavec-Merou 2024-01-19 07:37:55 +01:00
parent f00d49211b
commit 854541d5c7
1 changed files with 4 additions and 0 deletions
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litex/soc/cores/cpu/naxriscv/core.py
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@ -115,6 +115,7 @@ class NaxRiscv(CPU):
cpu_group.add_argument("--update-repo", default="recommended", choices=["latest","wipe+latest","recommended","wipe+recommended","no"], help="Specify how the NaxRiscv & SpinalHDL repo should be updated (latest: update to HEAD, recommended: Update to known compatible version, no: Don't update, wipe+*: Do clean&reset before checkout)") cpu_group.add_argument("--update-repo", default="recommended", choices=["latest","wipe+latest","recommended","wipe+recommended","no"], help="Specify how the NaxRiscv & SpinalHDL repo should be updated (latest: update to HEAD, recommended: Update to known compatible version, no: Don't update, wipe+*: Do clean&reset before checkout)")
cpu_group.add_argument("--no-netlist-cache", action="store_true", help="Always (re-)build the netlist.") cpu_group.add_argument("--no-netlist-cache", action="store_true", help="Always (re-)build the netlist.")
cpu_group.add_argument("--with-fpu", action="store_true", help="Enable the F32/F64 FPU.") cpu_group.add_argument("--with-fpu", action="store_true", help="Enable the F32/F64 FPU.")
cpu_group.add_argument("--with-rvc", action="store_true", help="Enable the Compress ISA extension.")
cpu_group.add_argument("--l2-bytes", default=128*1024, help="NaxRiscv L2 bytes, default 128 KB.") cpu_group.add_argument("--l2-bytes", default=128*1024, help="NaxRiscv L2 bytes, default 128 KB.")
cpu_group.add_argument("--l2-ways", default=8, help="NaxRiscv L2 ways, default 8.") cpu_group.add_argument("--l2-ways", default=8, help="NaxRiscv L2 ways, default 8.")
@ -127,6 +128,7 @@ class NaxRiscv(CPU):
NaxRiscv.update_repo = args.update_repo NaxRiscv.update_repo = args.update_repo
NaxRiscv.no_netlist_cache = args.no_netlist_cache NaxRiscv.no_netlist_cache = args.no_netlist_cache
NaxRiscv.with_fpu = args.with_fpu NaxRiscv.with_fpu = args.with_fpu
NaxRiscv.with_rvc = args.with_rvc
if args.scala_file: if args.scala_file:
NaxRiscv.scala_files = args.scala_file NaxRiscv.scala_files = args.scala_file
if args.scala_args: if args.scala_args:
@ -344,6 +346,8 @@ class NaxRiscv(CPU):
gen_args.append(f"--scala-file={file}") gen_args.append(f"--scala-file={file}")
if(NaxRiscv.with_fpu): if(NaxRiscv.with_fpu):
gen_args.append(f"--scala-args=rvf=true,rvd=true") gen_args.append(f"--scala-args=rvf=true,rvd=true")
if(NaxRiscv.with_rvc):
gen_args.append(f"--scala-args=rvc=true")
cmd = f"""cd {ndir} && sbt "runMain naxriscv.platform.litex.NaxGen {" ".join(gen_args)}\"""" cmd = f"""cd {ndir} && sbt "runMain naxriscv.platform.litex.NaxGen {" ".join(gen_args)}\""""
print("NaxRiscv generation command :") print("NaxRiscv generation command :")