framebuffer: process two pixels per system clock cycle
This commit is contained in:
Sebastien Bourdeauducq
parent
4dcec32010
commit
854c0461b4
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@ -1,45 +1,54 @@
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Instance
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from migen.fhdl.module import Module
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from migen.genlib.record import Record
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from migen.flow.actor import *
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from migen.flow.network import *
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from migen.flow.transactions import *
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from migen.flow import plumbing
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from migen.actorlib import misc, dma_asmi, structuring, sim, spi
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_hbits = 11
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_hbits = 10
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_vbits = 11
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_bpp = 32
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_bpc = 10
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_pixel_layout = [
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_pixel_layout_s = [
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("pad", _bpp-3*_bpc),
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("r", _bpc),
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("g", _bpc),
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("b", _bpc)
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]
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_pixel_layout = [
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("p0", _pixel_layout_s),
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("p1", _pixel_layout_s)
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]
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_bpc_dac = 8
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_dac_layout_s = [
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("r", _bpc_dac),
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("g", _bpc_dac),
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("b", _bpc_dac)
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]
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_dac_layout = [
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("hsync", 1),
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("vsync", 1),
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("r", _bpc_dac),
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("g", _bpc_dac),
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("b", _bpc_dac)
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("p0", _dac_layout_s),
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("p1", _dac_layout_s)
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]
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class _FrameInitiator(spi.SingleGenerator):
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def __init__(self, asmi_bits, length_bits, alignment_bits):
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layout = [
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("hres", _hbits, 640),
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("hsync_start", _hbits, 656),
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("hsync_end", _hbits, 752),
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("hscan", _hbits, 799),
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("hres", _hbits, 640, 1),
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("hsync_start", _hbits, 656, 1),
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("hsync_end", _hbits, 752, 1),
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("hscan", _hbits, 800, 1),
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("vres", _vbits, 480),
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("vsync_start", _vbits, 492),
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("vsync_end", _vbits, 494),
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("vscan", _vbits, 524),
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("vscan", _vbits, 525),
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("base", asmi_bits, 0, alignment_bits),
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("length", length_bits, 640*480*4, alignment_bits)
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@ -74,9 +83,8 @@ class VTG(Module, Actor):
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self.comb += [
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active.eq(hactive & vactive),
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If(active,
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self.token("dac").r.eq(self.token("pixels").r[skip:]),
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self.token("dac").g.eq(self.token("pixels").g[skip:]),
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self.token("dac").b.eq(self.token("pixels").b[skip:])
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[getattr(getattr(self.token("dac"), p), c).eq(getattr(getattr(self.token("pixels"), p), c)[skip:])
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for p in ["p0", "p1"] for c in ["r", "g", "b"]]
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),
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generate_en.eq(self.endpoints["timing"].stb & (~active | self.endpoints["pixels"].stb)),
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@ -122,9 +130,10 @@ class FIFO(Module, Actor):
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###
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data_width = 2+3*_bpc_dac
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data_width = 2+2*3*_bpc_dac
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fifo_full = Signal()
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fifo_write_en = Signal()
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fifo_read_en = Signal()
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fifo_data_out = Signal(data_width)
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fifo_data_in = Signal(data_width)
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self.specials += Instance("asfifo",
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@ -133,7 +142,7 @@ class FIFO(Module, Actor):
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Instance.Output("data_out", fifo_data_out),
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Instance.Output("empty"),
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Instance.Input("read_en", 1),
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Instance.Input("read_en", fifo_read_en),
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Instance.Input("clk_read", ClockSignal("vga")),
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Instance.Input("data_in", fifo_data_in),
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@ -142,17 +151,33 @@ class FIFO(Module, Actor):
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Instance.Input("clk_write", ClockSignal()),
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Instance.Input("rst", 0))
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t = self.token("dac")
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fifo_in = self.token("dac")
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fifo_out = Record(_dac_layout)
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self.comb += [
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Cat(self.vga_hsync_n, self.vga_vsync_n, self.vga_r, self.vga_g, self.vga_b).eq(fifo_data_out),
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self.endpoints["dac"].ack.eq(~fifo_full),
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fifo_write_en.eq(self.endpoints["dac"].stb),
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fifo_data_in.eq(Cat(~t.hsync, ~t.vsync, t.r, t.g, t.b)),
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fifo_data_in.eq(Cat(*fifo_in.flatten())),
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Cat(*fifo_out.flatten()).eq(fifo_data_out),
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self.busy.eq(0)
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]
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pix_parity = Signal()
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self.sync.vga += [
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pix_parity.eq(~pix_parity),
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self.vga_hsync_n.eq(~fifo_out.hsync),
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self.vga_vsync_n.eq(~fifo_out.vsync),
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If(pix_parity,
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self.vga_r.eq(fifo_out.p1.r),
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self.vga_g.eq(fifo_out.p1.g),
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self.vga_b.eq(fifo_out.p1.b)
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).Else(
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self.vga_r.eq(fifo_out.p0.r),
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self.vga_g.eq(fifo_out.p0.g),
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self.vga_b.eq(fifo_out.p0.b)
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)
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]
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self.comb += fifo_read_en.eq(pix_parity)
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def sim_fifo_gen():
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while True:
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t = Token("dac")
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@ -165,7 +190,7 @@ class Framebuffer(Module):
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asmi_bits = asmiport.hub.aw
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alignment_bits = bits_for(asmiport.hub.dw//8) - 1
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length_bits = _hbits + _vbits + 2 - alignment_bits
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pack_factor = asmiport.hub.dw//_bpp
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pack_factor = asmiport.hub.dw//(2*_bpp)
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packed_pixels = structuring.pack_layout(_pixel_layout, pack_factor)
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fi = _FrameInitiator(asmi_bits, length_bits, alignment_bits)
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