Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

targets/versa_ecp5: increase sys_clk_freq to 50MHz

This commit is contained in:
Florent Kermarrec 2018-11-12 10:12:10 +01:00
parent a752dafb14
commit 8574c62f75
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/boards/targets/versa_ecp5.py
View File

@ -28,7 +28,7 @@ class _CRG(Module):
# sys_4x_clk divider # sys_4x_clk divider
self.comb += self.cd_sys_4x.clk.eq(clk100) self.comb += self.cd_sys_4x.clk.eq(clk100)
sys_4x_divider = Signal(2) sys_4x_divider = Signal(1)
self.sync.sys_4x += sys_4x_divider.eq(sys_4x_divider + 1) self.sync.sys_4x += sys_4x_divider.eq(sys_4x_divider + 1)
# sys_clk # sys_clk
@ -40,7 +40,7 @@ class _CRG(Module):
# sys_clk phase shifted (for sdram) # sys_clk phase shifted (for sdram)
sdram_ps_clk = self.cd_sys.clk sdram_ps_clk = self.cd_sys.clk
# FIXME: phase shift with luts, needs PLL support. # FIXME: phase shift with luts, needs PLL support.
sdram_ps_luts = 5 sdram_ps_luts = 2
for i in range(sdram_ps_luts): for i in range(sdram_ps_luts):
new_sdram_ps_clk = Signal() new_sdram_ps_clk = Signal()
self.specials += Instance("LUT4", self.specials += Instance("LUT4",
@ -60,7 +60,7 @@ class BaseSoC(SoCSDRAM):
def __init__(self, **kwargs): def __init__(self, **kwargs):
platform = versa_ecp5.Platform(toolchain="prjtrellis") platform = versa_ecp5.Platform(toolchain="prjtrellis")
platform.add_extension(versa_ecp5._ecp5_soc_hat_io) platform.add_extension(versa_ecp5._ecp5_soc_hat_io)
sys_clk_freq = int(25e6) sys_clk_freq = int(50e6)
SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq, SoCSDRAM.__init__(self, platform, clk_freq=sys_clk_freq,
l2_size=32, l2_size=32,
integrated_rom_size=0x8000, integrated_rom_size=0x8000,