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bios/sdram: add some margin on cdly ideal_delay, do the read_leveling even if write_leveling is not optimal. 

We need to provide enough information to ease support and understand the issue. The write leveling/read leveling
are doing there best to calibrate the DRAM correctly and memtest gives the final result.
This commit is contained in:
Florent Kermarrec 2020-04-25 12:11:10 +02:00
parent 038e1bc048
commit 85a059bf77
1 changed files with 3 additions and 5 deletions
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8
litex/soc/software/bios/sdram.c
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@ -442,7 +442,7 @@ static void write_level_cdly_range(unsigned int *best_error, int *best_cdly,
delay_mean /= SDRAM_PHY_MODULES;
/* we want it to be at the start */
int ideal_delay = 1;
int ideal_delay = 4*SDRAM_PHY_DELAYS/32;
int error = ideal_delay - delay_mean;
if (error < 0)
error *= -1;
@ -1069,13 +1069,11 @@ int sdrlevel(void)
#ifdef SDRAM_PHY_WRITE_LEVELING_CAPABLE
printf("Write leveling:\n");
if (_write_level_cdly_scan) {
if(!write_level())
return 0;
write_level();
} else {
/* use only the current cdly */
int delays[SDRAM_PHY_MODULES];
if (!write_level_scan(delays, 1))
return 0;
write_level_scan(delays, 1);
}
#endif