sdramphy/initsequence: fix and add format_mr0 function
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@ -161,29 +161,37 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
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bl = 2*sdram_phy.phy_settings.nphases
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bl = 2*sdram_phy.phy_settings.nphases
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if bl != 8:
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if bl != 8:
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raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
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raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
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cl_to_mr0 = {
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5 : 0b0010,
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def format_mr0(cl, wr, dll_reset):
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6 : 0b0100,
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cl_to_mr0 = {
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7 : 0b0110,
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5 : 0b0010,
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8 : 0b1000,
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6 : 0b0100,
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9 : 0b1010,
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7 : 0b0110,
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10: 0b1100,
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8 : 0b1000,
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11: 0b1110,
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9 : 0b1010,
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12: 0b0001,
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10: 0b1100,
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13: 0b0011,
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11: 0b1110,
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14: 0b0101
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12: 0b0001,
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}
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13: 0b0011,
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wr_to_mr0 = {
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14: 0b0101
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16: 0b000,
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}
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5 : 0b001,
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wr_to_mr0 = {
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6 : 0b010,
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16: 0b000,
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7 : 0b011,
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5 : 0b001,
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8 : 0b100,
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6 : 0b010,
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10: 0b101,
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7 : 0b011,
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12: 0b110,
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8 : 0b100,
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14: 0b111
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10: 0b101,
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}
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12: 0b110,
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mr0 = cl_to_mr0[cl] << 4 | 1 << 8 | wr_to_mr0[8] # FIXME: this should be ceiling(tWR/tCK)
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14: 0b111
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}
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mr0 = (cl_to_mr0[cl] & 1) << 2
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mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
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mr0 |= dll_reset << 8
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mr0 |= wr_to_mr0[wr] << 9
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return mr0
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mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
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mr1 = 6 # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
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mr1 = 6 # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
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mr2 = (sdram_phy.phy_settings.cwl-5) << 3
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mr2 = (sdram_phy.phy_settings.cwl-5) << 3
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mr3 = 0
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mr3 = 0
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