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sdramphy/initsequence: fix and add format_mr0 function

This commit is contained in:
Florent Kermarrec 2014-08-13 16:44:20 +02:00 committed by Sebastien Bourdeauducq
parent 9844c25df9
commit 85b29c883a
1 changed files with 31 additions and 23 deletions
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54
misoclib/sdramphy/initsequence.py
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@ -161,29 +161,37 @@ const unsigned int dfii_pix_rddata_addr[{n}] = {{
bl = 2*sdram_phy.phy_settings.nphases bl = 2*sdram_phy.phy_settings.nphases
if bl != 8: if bl != 8:
raise NotImplementedError("DDR3 PHY header generator only supports BL of 8") raise NotImplementedError("DDR3 PHY header generator only supports BL of 8")
cl_to_mr0 = {
5 : 0b0010, def format_mr0(cl, wr, dll_reset):
6 : 0b0100, cl_to_mr0 = {
7 : 0b0110, 5 : 0b0010,
8 : 0b1000, 6 : 0b0100,
9 : 0b1010, 7 : 0b0110,
10: 0b1100, 8 : 0b1000,
11: 0b1110, 9 : 0b1010,
12: 0b0001, 10: 0b1100,
13: 0b0011, 11: 0b1110,
14: 0b0101 12: 0b0001,
} 13: 0b0011,
wr_to_mr0 = { 14: 0b0101
16: 0b000, }
5 : 0b001, wr_to_mr0 = {
6 : 0b010, 16: 0b000,
7 : 0b011, 5 : 0b001,
8 : 0b100, 6 : 0b010,
10: 0b101, 7 : 0b011,
12: 0b110, 8 : 0b100,
14: 0b111 10: 0b101,
} 12: 0b110,
mr0 = cl_to_mr0[cl] << 4 | 1 << 8 | wr_to_mr0[8] # FIXME: this should be ceiling(tWR/tCK) 14: 0b111
}
mr0 = (cl_to_mr0[cl] & 1) << 2
mr0 |= ((cl_to_mr0[cl] >> 1) & 0b111) << 4
mr0 |= dll_reset << 8
mr0 |= wr_to_mr0[wr] << 9
return mr0
mr0 = format_mr0(cl, 8, 1) # wr=8 FIXME: this should be ceiling(tWR/tCK)
mr1 = 6 # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm) mr1 = 6 # Output Drive Strength RZQ/7 (34 ohm) / Rtt RZQ/4 (60 ohm)
mr2 = (sdram_phy.phy_settings.cwl-5) << 3 mr2 = (sdram_phy.phy_settings.cwl-5) << 3
mr3 = 0 mr3 = 0