build/anlogic: Minor cosmetic cleanups.
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@ -56,6 +56,7 @@ def _build_al(name, family, device, files):
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xml = []
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date = datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")
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# Set Device.
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xml.append(f"<?xml version=\"1.0\" encoding=\"UTF-8\"?>")
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xml.append(f"<Project Version=\"1\" Path=\"...\">")
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@ -69,6 +70,7 @@ def _build_al(name, family, device, files):
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xml.append(f" </HardWare>")
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xml.append(f" <Source_Files>")
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xml.append(f" <Verilog>")
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# Add Sources.
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for f, typ, lib in files:
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xml.append(f" <File Path=\"{f}\">")
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@ -139,7 +141,8 @@ def _build_tcl(name, architecture, package):
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# Add project.
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tcl.append(f"open_project {name}.al")
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# Rlaborate
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# Elaborate.
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tcl.append(f"elaborate -top {name}")
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# Add IOs Constraints.
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@ -150,7 +153,7 @@ def _build_tcl(name, architecture, package):
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# Add SDC Constraints.
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tcl.append("read_sdc top.sdc")
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# Perform PnR
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# Perform PnR.
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tcl.append("optimize_gate")
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tcl.append("legalize_phy_inst")
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tcl.append("place")
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@ -192,13 +195,13 @@ class TangDinastyToolchain:
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cwd = os.getcwd()
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os.makedirs(build_dir, exist_ok=True)
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os.chdir(build_dir)
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# Finalize design
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# Finalize design.
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
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platform.finalize(fragment)
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# Generate verilog
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# Generate verilog.
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v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
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named_sc, named_pc = platform.resolve_signals(v_output.ns)
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v_file = build_name + ".v"
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@ -212,27 +215,28 @@ class TangDinastyToolchain:
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named_pc = named_pc
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)
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# Timings (.sdc)
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# Timings (.sdc).
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_build_sdc(
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clocks = self.clocks,
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vns = v_output.ns
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)
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architecture, family, package = parse_device(platform.device)
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# Generate project file (.al)
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# Generate project file (.al).
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al = _build_al(
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name = build_name,
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family = family,
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device = platform.device,
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files = platform.sources)
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# Generate build script (.tcl)
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# Generate build script (.tcl).
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script = _build_tcl(
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name = build_name,
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architecture = architecture,
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package = package)
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# Run
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# Run.
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if run:
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if which("td") is None:
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msg = "Unable to find Tang Dinasty toolchain, please:\n"
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@ -18,27 +18,28 @@ class AnlogicAsyncResetSynchronizerImpl(Module):
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self.specials += [
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Instance("AL_MAP_SEQ",
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p_DFFMODE = "FF",
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p_REGSET = "SET",
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p_SRMUX = "SR",
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p_SRMODE = "ASYNC",
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i_ce = 1,
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i_d = 0,
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i_sr = async_reset,
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i_clk = cd.clk,
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o_q = rst1),
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p_REGSET = "SET",
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p_SRMUX = "SR",
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p_SRMODE = "ASYNC",
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i_ce = 1,
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i_d = 0,
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i_sr = async_reset,
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i_clk = cd.clk,
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o_q = rst1
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),
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Instance("AL_MAP_SEQ",
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p_DFFMODE = "FF",
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p_REGSET = "SET",
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p_SRMUX = "SR",
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p_SRMODE = "ASYNC",
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i_ce = 1,
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i_d = rst1,
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i_sr = async_reset,
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i_clk = cd.clk,
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o_q = cd.rst)
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p_REGSET = "SET",
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p_SRMUX = "SR",
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p_SRMODE = "ASYNC",
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i_ce = 1,
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i_d = rst1,
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i_sr = async_reset,
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i_clk = cd.clk,
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o_q = cd.rst
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)
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]
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class AnlogicAsyncResetSynchronizer:
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@staticmethod
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def lower(dr):
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