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build/anlogic: Minor cosmetic cleanups.

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This commit is contained in:
Florent Kermarrec 2021-11-23 19:12:31 +01:00
parent c2d6ea97fa
commit 85d6cb4b8d
2 changed files with 30 additions and 25 deletions
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20
litex/build/anlogic/anlogic.py
View file

@ -56,6 +56,7 @@ def _build_al(name, family, device, files):
xml = [] xml = []
date = datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S") date = datetime.datetime.now().strftime("%Y-%m-%d %H:%M:%S")
# Set Device. # Set Device.
xml.append(f"<?xml version=\"1.0\" encoding=\"UTF-8\"?>") xml.append(f"<?xml version=\"1.0\" encoding=\"UTF-8\"?>")
xml.append(f"<Project Version=\"1\" Path=\"...\">") xml.append(f"<Project Version=\"1\" Path=\"...\">")
@ -69,6 +70,7 @@ def _build_al(name, family, device, files):
xml.append(f" </HardWare>") xml.append(f" </HardWare>")
xml.append(f" <Source_Files>") xml.append(f" <Source_Files>")
xml.append(f" <Verilog>") xml.append(f" <Verilog>")
# Add Sources. # Add Sources.
for f, typ, lib in files: for f, typ, lib in files:
xml.append(f" <File Path=\"{f}\">") xml.append(f" <File Path=\"{f}\">")
@ -139,7 +141,8 @@ def _build_tcl(name, architecture, package):
# Add project. # Add project.
tcl.append(f"open_project {name}.al") tcl.append(f"open_project {name}.al")
# Rlaborate
# Elaborate.
tcl.append(f"elaborate -top {name}") tcl.append(f"elaborate -top {name}")
# Add IOs Constraints. # Add IOs Constraints.
@ -150,7 +153,7 @@ def _build_tcl(name, architecture, package):
# Add SDC Constraints. # Add SDC Constraints.
tcl.append("read_sdc top.sdc") tcl.append("read_sdc top.sdc")
# Perform PnR # Perform PnR.
tcl.append("optimize_gate") tcl.append("optimize_gate")
tcl.append("legalize_phy_inst") tcl.append("legalize_phy_inst")
tcl.append("place") tcl.append("place")
@ -192,13 +195,13 @@ class TangDinastyToolchain:
cwd = os.getcwd() cwd = os.getcwd()
os.makedirs(build_dir, exist_ok=True) os.makedirs(build_dir, exist_ok=True)
os.chdir(build_dir) os.chdir(build_dir)
# Finalize design
# Finalize design.
if not isinstance(fragment, _Fragment): if not isinstance(fragment, _Fragment):
fragment = fragment.get_fragment() fragment = fragment.get_fragment()
platform.finalize(fragment) platform.finalize(fragment)
# Generate verilog # Generate verilog.
v_output = platform.get_verilog(fragment, name=build_name, **kwargs) v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
named_sc, named_pc = platform.resolve_signals(v_output.ns) named_sc, named_pc = platform.resolve_signals(v_output.ns)
v_file = build_name + ".v" v_file = build_name + ".v"
@ -212,27 +215,28 @@ class TangDinastyToolchain:
named_pc = named_pc named_pc = named_pc
) )
# Timings (.sdc) # Timings (.sdc).
_build_sdc( _build_sdc(
clocks = self.clocks, clocks = self.clocks,
vns = v_output.ns vns = v_output.ns
) )
architecture, family, package = parse_device(platform.device) architecture, family, package = parse_device(platform.device)
# Generate project file (.al)
# Generate project file (.al).
al = _build_al( al = _build_al(
name = build_name, name = build_name,
family = family, family = family,
device = platform.device, device = platform.device,
files = platform.sources) files = platform.sources)
# Generate build script (.tcl) # Generate build script (.tcl).
script = _build_tcl( script = _build_tcl(
name = build_name, name = build_name,
architecture = architecture, architecture = architecture,
package = package) package = package)
# Run # Run.
if run: if run:
if which("td") is None: if which("td") is None:
msg = "Unable to find Tang Dinasty toolchain, please:\n" msg = "Unable to find Tang Dinasty toolchain, please:\n"

35
litex/build/anlogic/common.py
View file

@ -18,27 +18,28 @@ class AnlogicAsyncResetSynchronizerImpl(Module):
self.specials += [ self.specials += [
Instance("AL_MAP_SEQ", Instance("AL_MAP_SEQ",
p_DFFMODE = "FF", p_DFFMODE = "FF",
p_REGSET = "SET", p_REGSET = "SET",
p_SRMUX = "SR", p_SRMUX = "SR",
p_SRMODE = "ASYNC", p_SRMODE = "ASYNC",
i_ce = 1, i_ce = 1,
i_d = 0, i_d = 0,
i_sr = async_reset, i_sr = async_reset,
i_clk = cd.clk, i_clk = cd.clk,
o_q = rst1), o_q = rst1
),
Instance("AL_MAP_SEQ", Instance("AL_MAP_SEQ",
p_DFFMODE = "FF", p_DFFMODE = "FF",
p_REGSET = "SET", p_REGSET = "SET",
p_SRMUX = "SR", p_SRMUX = "SR",
p_SRMODE = "ASYNC", p_SRMODE = "ASYNC",
i_ce = 1, i_ce = 1,
i_d = rst1, i_d = rst1,
i_sr = async_reset, i_sr = async_reset,
i_clk = cd.clk, i_clk = cd.clk,
o_q = cd.rst) o_q = cd.rst
)
] ]
class AnlogicAsyncResetSynchronizer: class AnlogicAsyncResetSynchronizer:
@staticmethod @staticmethod
def lower(dr): def lower(dr):