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Merge pull request #1526 from gsomlo/gls-mem-axi-width-warn 

integration/soc: Warn on MemBus <-> LiteDRAM AXI width conversion
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enjoy-digital 2022-12-03 21:58:54 +01:00 committed by GitHub
parent fe7e70baa9 be40e796f2
commit 85f762cd1c
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litex/soc/integration/soc.py
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@ -1529,6 +1529,10 @@ class LiteXSoC(SoC):
# Check if bus is an AXI bus and connect it. # Check if bus is an AXI bus and connect it.
if isinstance(mem_bus, axi.AXIInterface): if isinstance(mem_bus, axi.AXIInterface):
data_width_ratio = int(port.data_width/mem_bus.data_width) data_width_ratio = int(port.data_width/mem_bus.data_width)
if data_width_ratio != 1:
self.logger.warning("Converting MemBus({}) data width to LiteDRAM({}).".format(
colorer(mem_bus.data_width, color="yellow"),
colorer(port.data_width, color="yellow")))
# If same data_width, connect it directly. # If same data_width, connect it directly.
if data_width_ratio == 1: if data_width_ratio == 1:
self.submodules += LiteDRAMAXI2Native( self.submodules += LiteDRAMAXI2Native(