fhdl/verilog: Update Reserved Keywords (from IEEE 1800-2017) and minor cleanup.
This commit is contained in:
Florent Kermarrec
parent
adf30928d4
commit
86178ed2d9
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@ -27,28 +27,62 @@ from migen.fhdl.specials import Memory
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from litex.gen.fhdl.memory import memory_emit_verilog
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from litex.build.tools import generated_banner
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# Reserved Keywords -------------------------------------------------------------------------------
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_reserved_keywords = {
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"always", "and", "assign", "automatic", "begin", "buf", "bufif0", "bufif1",
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"case", "casex", "casez", "cell", "cmos", "config", "deassign", "default",
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"defparam", "design", "disable", "edge", "else", "end", "endcase",
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"endconfig", "endfunction", "endgenerate", "endmodule", "endprimitive",
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"endspecify", "endtable", "endtask", "event", "for", "force", "forever",
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"fork", "function", "generate", "genvar", "highz0", "highz1", "if",
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"ifnone", "incdir", "include", "initial", "inout", "input",
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"instance", "integer", "join", "large", "liblist", "library", "localparam",
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"macromodule", "medium", "module", "nand", "negedge", "nmos", "nor",
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"noshowcancelled", "not", "notif0", "notif1", "or", "output", "parameter",
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"pmos", "posedge", "primitive", "pull0", "pull1" "pulldown",
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"pullup", "pulsestyle_onevent", "pulsestyle_ondetect", "remos", "real",
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"realtime", "reg", "release", "repeat", "rnmos", "rpmos", "rtran",
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"rtranif0", "rtranif1", "scalared", "showcancelled", "signed", "small",
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"specify", "specparam", "strong0", "strong1", "supply0", "supply1",
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"table", "task", "time", "tran", "tranif0", "tranif1", "tri", "tri0",
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"tri1", "triand", "trior", "trireg", "unsigned", "use", "vectored", "wait",
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"wand", "weak0", "weak1", "while", "wire", "wor","xnor", "xor", "do"
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_ieee_1800_2017_verilog_reserved_keywords = {
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"accept_on", "alias", "always", "always_comb", "always_ff",
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"always_latch", "and", "assert", "assign", "assume",
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"automatic", "before", "begin", "bind", "bins",
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"binsof", "bit", "break", "buf", "bufif0",
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"bufif1", "byte", "case", "casex", "casez",
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"cell", "chandle", "checker", "class", "clocking",
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"cmos", "config", "const", "constraint", "context",
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"continue", "cover", "covergroup", "coverpoint", "cross",
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"deassign", "default", "defparam", "design", "disable",
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"dist", "do", "edge", "else", "end",
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"endcase", "endchecker", "endclass", "endclocking", "endconfig",
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"endfunction", "endgenerate", "endgroup", "endinterface", "endmodule",
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"endpackage", "endprimitive", "endprogram", "endproperty", "endsequence",
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"endspecify", "endtable", "endtask", "enum", "event",
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"eventually", "expect", "export", "extends", "extern",
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"final", "first_match", "for", "force", "foreach",
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"forever", "fork", "forkjoin", "function", "generate",
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"genvar", "global", "highz0", "highz1", "if",
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"iff", "ifnone", "ignore_bins", "illegal_bins", "implements",
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"implies", "import", "incdir", "include", "initial",
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"inout", "input", "inside", "instance", "int",
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"integer", "interconnect", "interface", "intersect", "join",
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"join_any", "join_none", "large", "let", "liblist",
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"library", "local", "localparam", "logic", "longint",
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"macromodule", "matches", "medium", "modport", "module",
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"nand", "negedge", "nettype", "new", "nexttime",
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"nmos", "nor", "noshowcancelled", "not", "notif0",
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"notif1", "null", "or", "output", "package",
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"packed", "parameter", "pmos", "posedge", "primitive",
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"priority", "program", "property", "protected", "pull0",
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"pull1", "pulldown", "pullup", "pulsestyle_ondetect", "pulsestyle_onevent",
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"pure", "rand", "randc", "randcase", "randsequence",
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"rcmos", "real", "realtime", "ref", "reg",
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"reject_on", "release", " repeat", "restrict", "return",
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"rnmos", "rpmos", "rtran", "rtranif0", "rtranif1",
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"s_always", "s_eventually", "s_nexttime", "s_until", "s_until_with",
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"scalared", "sequence", "shortint", "shortreal", "showcancelled",
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"signed", "small", "soft", "solve", "specify",
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"specparam", "static", "string", "strong", "strong0",
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"strong1", "struct", "super", "supply0", "supply1",
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"sync_accept_on", "sync_reject_on", "table", "tagged", "task",
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"this", "throughout", "time", "timeprecision", "timeunit",
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"tran", "tranif0", "tranif1", "tri", "tri0",
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"tri1", "triand", "trior", "trireg", "type",
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"typedef", " union", "unique", "unique0", "unsigned",
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"until", "until_with", "untyped", "use", " uwire",
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"var", "vectored", "virtual", "void", "wait",
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"wait_order", "wand", "weak", "weak0", "weak1",
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"while", "wildcard", "wire", "with", "within",
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"wor", "xnor", "xor",
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}
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# Print Signals ------------------------------------------------------------------------------------
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def _printsig(ns, s):
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if s.signed:
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@ -60,6 +94,7 @@ def _printsig(ns, s):
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n += ns.get_name(s)
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return n
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# Print Constants ----------------------------------------------------------------------------------
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def _printconstant(node):
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if node.signed:
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@ -68,6 +103,7 @@ def _printconstant(node):
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else:
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return str(node.nbits) + "'d" + str(node.value), False
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# Print Expressions --------------------------------------------------------------------------------
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def _printexpr(ns, node):
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if isinstance(node, Constant):
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@ -131,6 +167,8 @@ def _printexpr(ns, node):
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raise TypeError("Expression of unrecognized type: '{}'".format(type(node).__name__))
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# Print Nodes --------------------------------------------------------------------------------------
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(_AT_BLOCKING, _AT_NONBLOCKING, _AT_SIGNAL) = range(3)
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@ -188,14 +226,7 @@ def _printnode(ns, at, level, node, target_filter=None):
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else:
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raise TypeError("Node of unrecognized type: "+str(type(node)))
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def _list_comb_wires(f):
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r = set()
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groups = group_by_targets(f.comb)
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for g in groups:
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r |= g[0]
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return r
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# Print Attributes ---------------------------------------------------------------------------------
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def _printattr(attr, attr_translate):
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r = ""
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@ -220,6 +251,15 @@ def _printattr(attr, attr_translate):
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r = "(* " + r + " *)"
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return r
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# Print Header -------------------------------------------------------------------------------------
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def _list_comb_wires(f):
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r = set()
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groups = group_by_targets(f.comb)
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for g in groups:
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if len(g[1]) == 1 and isinstance(g[1][0], _Assign):
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r |= g[0]
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return r
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def _printheader(f, ios, name, ns, attr_translate,
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reg_initialization):
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@ -267,6 +307,7 @@ def _printheader(f, ios, name, ns, attr_translate,
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r += "\n"
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return r
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# Print Combinatorial Logic (Simulation) -----------------------------------------------------------
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def _printcomb_simulation(f, ns,
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display_run,
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@ -325,6 +366,7 @@ def _printcomb_simulation(f, ns,
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r += "\n"
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return r
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# Print Combinatorial Logic (Synthesis) ------------------------------------------------------------
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def _printcomb_regular(f, ns, blocking_assign):
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r = ""
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@ -348,6 +390,7 @@ def _printcomb_regular(f, ns, blocking_assign):
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r += "\n"
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return r
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# Print Synchronous Logic --------------------------------------------------------------------------
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def _printsync(f, ns):
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r = ""
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@ -357,6 +400,7 @@ def _printsync(f, ns):
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r += "end\n\n"
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return r
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# Print Specials -----------------------------------------------------------------------------------
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def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
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r = ""
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@ -375,21 +419,21 @@ def _printspecials(overrides, specials, ns, add_data_file, attr_translate):
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r += pr
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return r
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# Convert FHDL to Verilog ------------------------------------------------------------------------
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class DummyAttrTranslate(dict):
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def __getitem__(self, k):
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return (k, "true")
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def convert(f, ios=None, name="top",
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special_overrides=dict(),
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attr_translate=DummyAttrTranslate(),
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create_clock_domains=True,
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display_run=False,
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reg_initialization=True,
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dummy_signal=True,
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blocking_assign=False,
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regular_comb=True):
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special_overrides = dict(),
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attr_translate = DummyAttrTranslate(),
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create_clock_domains = True,
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display_run = False,
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reg_initialization = True,
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dummy_signal = True,
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blocking_assign = False,
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regular_comb = True):
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r = ConvOutput()
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if not isinstance(f, _Fragment):
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f = f.get_fragment()
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@ -423,7 +467,7 @@ def convert(f, ios=None, name="top",
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io.name_override = io_name
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ns = build_namespace(list_signals(f) \
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| list_special_ios(f, True, True, True) \
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| ios, _reserved_keywords)
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| ios, _ieee_1800_2017_verilog_reserved_keywords)
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ns.clock_domains = f.clock_domains
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r.ns = ns
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