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integration/soc/add_uartbone: fix jtag_uart integration.

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This commit is contained in:
Florent Kermarrec 2021-01-22 15:00:01 +01:00
parent d7aedfbc12
commit 8623b0a16a
1 changed files with 4 additions and 5 deletions
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9
litex/soc/integration/soc.py
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@ -1163,16 +1163,15 @@ class LiteXSoC(SoC):
# Add UARTbone --------------------------------------------------------------------------------- # Add UARTbone ---------------------------------------------------------------------------------
def add_uartbone(self, name="serial", clk_freq=None, baudrate=115200, cd="sys"): def add_uartbone(self, name="serial", clk_freq=None, baudrate=115200, cd="sys"):
from litex.soc.cores import uart from litex.soc.cores import uart
if clk_freq is None:
clk_freq = self.sys_clk_freq
if name == "jtag_uart": if name == "jtag_uart":
from litex.soc.cores.jtag import JTAGPHY from litex.soc.cores.jtag import JTAGPHY
phy = JTAGPHY(device=self.platform.device) phy = JTAGPHY(device=self.platform.device)
else: else:
phy = uart.UARTPHY(platform.request(name), clk_freq, bandrate) phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
self.submodules += phy self.submodules += phy
self.submodules.uartbone = uart.UARTBone( self.submodules.uartbone = uart.UARTBone(phy=phy, clk_freq=clk_freq, cd=cd)
phy = phy,
clk_freq = clk_freq if clk_freq is not None else self.sys_clk_freq,
cd = cd)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone) self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# Add SDRAM ------------------------------------------------------------------------------------ # Add SDRAM ------------------------------------------------------------------------------------