doc: fix typos
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README
4
README
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@ -106,7 +106,7 @@ devel [AT] lists.m-labs.hk.
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python3 bist.py
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python3 bist.py
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[> Simulations:
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[> Simulations:
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Simulations are avalaible in ./lib/sata/test:
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Simulations are available in ./lib/sata/test:
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- crc_tb
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- crc_tb
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- scrambler_tb
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- scrambler_tb
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- phy_datapath_tb
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- phy_datapath_tb
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@ -118,7 +118,7 @@ devel [AT] lists.m-labs.hk.
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make simulation_name
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make simulation_name
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[> Tests :
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[> Tests :
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A synthetisable BIST is provided and can be controlled with ./test/bist.py
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A synthetizable BIST is provided and can be controlled with ./test/bist.py
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By using Miscope and the provided ./test/test_link.py example you are able to
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By using Miscope and the provided ./test/test_link.py example you are able to
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visualize the internal logic of the design and even inject the captured data in
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visualize the internal logic of the design and even inject the captured data in
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the HDD model!
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the HDD model!
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@ -4,7 +4,7 @@
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Simulation
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Simulation
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========================
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========================
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Simulations are avalaible in ./lib/sata/test:
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Simulations are available in ./lib/sata/test:
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- crc_tb
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- crc_tb
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- scrambler_tb
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- scrambler_tb
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- phy_datapath_tb
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- phy_datapath_tb
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@ -4,7 +4,7 @@
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Test
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Test
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========================
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========================
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A synthetisable BIST is provided and can be controlled with ./test/bist.py.
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A synthetizable BIST is provided and can be controlled with ./test/bist.py.
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By using Miscope and the provided ./test/test_link.py example you are able to
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By using Miscope and the provided ./test/test_link.py example you are able to
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visualize the internal logic of the design and even inject the captured data in
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visualize the internal logic of the design and even inject the captured data in
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the HDD model!
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the HDD model!
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