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interconnect/csr_bus: fix paged access warning

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Ilia Sergachev 2020-07-20 18:23:09 +02:00
parent 4a18b828bc
commit 8656ea9b67
1 changed files with 1 additions and 1 deletions
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2
litex/soc/interconnect/csr_bus.py
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@ -100,7 +100,7 @@ class SRAM(Module):
page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False) page_bits = log2_int((mem.depth*csrw_per_memw + aligned_paging - 1)//aligned_paging, False)
if page_bits: if page_bits:
self._page = CSRStorage(page_bits, name=mem.name_override + "_page") self._page = CSRStorage(page_bits, name=mem.name_override + "_page")
printf("WARNING: SRAM CSR memory will requires paged access.") print("WARNING: SRAM CSR memory will require paged access.")
else: else:
self._page = None self._page = None
if read_only is None: if read_only is None: